SM8521 datasheet(25/56 Pages) SHARP

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SM8521

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PS1 (Interrupt enable bit (I) of processor status 1)

The bit I (bit 0 : PS1) enables/disables all maskable

interrupts. After hardware reset, the bit I is set ‘0’

and so all maskable interrupts are in disable state.

Bit 0 : Interrupt enable (I)

Except that write to processor status PS1 directly,

the bit I can be set/cleared by the following special-

purpose instructions. (Under normal case, the

special-purpose instructions are used.)

DI instruction : bit I is set ‘0’.

EI instruction : bit I is set ‘1’.

IE0 (Interrupt enable register 0)

The interrupt enable register IE0 is an 8-bit

readable/writable register containing the settings for

enable/disable to accept interrupt sources.

Bit 7

Bit 7 : DMA interrupt enable bit

Bit 6 : Timer 0 interrupt enable bit

Bit 5 : Sets ‘0’.

Bit 4 : External interrupt enable bit

Bit 3 : UART interrupt enable bit

Bits 2 to 1 : Set ‘0’.

Bit 0 : LCD cotroller interrupt enable bit

IE1 (Interrupt enable register 1)

The interrupt enable register IE1 is an 8-bit

readable/writable register containing the settings for

enable/disable to accept interrupt sources.

Bit 7

Bit 7 : Sets ‘0’.

Bit 6 : Timer 1 interrupt enable bit

Bit 5 : Sets ‘0’.

Bit 4 : Clock interrupt enable bit

Bit 3 : Sets ‘0’.

Bit 2 : PIO interrupt enable bit

Bits 1 to 0 : Set ‘0’.

The interrupt enable register IE0 and IE1 are also

used to wake up the chip from standby mode

(STOP mode, HALT mode) by setting the interrupt

to enable. If the interrupt enabled by the interrupt

enable register IE0 and IE1 occurs, the chip will

wake up from standby mode. But also there are

interrupt sources which cannot use to wake up

from STOP mode. For more details, refer to "Stand

by Function".

DMA TIM0

EXTINT UART

LCDC

TIM1

CLK

PIO

BIT

CONTENT

Disable

Enable

BIT

CONTENT

Disable

Enable

BIT

CONTENT

Disables to accept all maskable interrupts

Enables to accept maskable interrupt. For

each maskable interrupt can be enabled/

disabled by interrupt enable register IE0, IE1

and bits IM2-IM0.

SM8521 Datasheet(PDF) 25 Page - Sharp Corporation

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