SM8521 datasheet(17/56 Pages) SHARP

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SM8521

- 17 -

WRB

D0-D7

Valid data

tWSA

Invalid data

tWSD

tWHD

tWHA

tWWR

A0-A20

• External memory access timing (write timing)

Operating condition

(VDD = 4.5 to 5.5 V, TOPR = –10 to 60˚C)

PARAMETER

SYMBOL

UNIT

NOTE

Address setup time

tWSA

tSYS

tSYS + 50

Data setup time

tWSD

tSYS – 50

tSYS + 30

WRB signal pulse width

tWWR

tSYS – 60

tSYS

Address hold time

tWHA

Data hold time

tWHD

MIN.

TYP.

MAX.

NOTE :

1. tSYS : The system clock period (main clock x 1/2) when the

low order 3 bits in the clock change register

FCPUS2-FCPUS0 are 100B.

tWSA : The time between address firm and WRB signal

falling Low level firm.

tWSD : The time between WRB signal rising High level firm

and output valid data firm.

tWWR : WRB signal Low level width.

tWHA : The time between WRB signal rising High level firm

and address change.

tWHD : The time between WRB signal rising High level firm

and output data floating.

Load capacitance is 50 pF.

Fig. 6

External Memory Access Timing (Write Timing)

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