SM8521 datasheet(40/56 Pages) SHARP

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SM8521

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DMBR (ROM bank register)

DMBR register specifies ROM's bank being

transferred. (Organization of bank is 256 x 256

dots. Bank specifies external memory address

irrespective of MMU.)

Bit 7

DMVP(DMVP register)

DMVP register specifies a page (VRAM) in case of

specifying VRAM to source and destination.

Bit 7

Bits 7 to 2 : Set ‘0’.

Bit 1 : Destination page A/B

Bit 0 : Source page A/B

DMPL (Pallet register)

DMPL register specifies gradation to dot data.

When transferring, gradation data concerned with

dot data of the DMPL register is stored to VRAM.

Bit 7

Bits 7 to 6 : Dot data color 0

Bits 5 to 4 : Dot data color 1

Bits 3 to 2 : Dot data color 2

Bits 1 to 0 : Dot data color 3

Example :

When dot data color 2 (10B) is specified under the

status of the DMPL register filled with

∗∗01∗∗∗∗B,

bit 4 and 5 of the DMPL register are automatically

selected. Dot data changes from color 2 (10B) to

color 1 (01B). Then the dot data color 1 moves to

specified VRAM.

COL31COL30 COL21 COL20 COL11 COL10 COL01 COL00

DMPL

NOTE : Color 0-3 are not depth gradation. Depth of black and white on LCD is fixed by Gradiation control bit of the LCC register.

ROM/VRAM

Dot data = color 2 (10B)

Color 3

Color 2

Color 1

Color 0

VRAM

Dot data = color 1 (01B)

Fig. 18

How to Select Gradations

DMBR6 DMBR5 DMBR4 DMBR3 DMBR2 DMBR1 DMBR0

------

SOUAB DESAB

BIT

CONTENT

Destination page A

Destination page B

BIT

CONTENT

Source page A

Source page B

SM8521 Datasheet(PDF) 40 Page - Sharp Corporation

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