SM8521 datasheet(48/56 Pages) SHARP

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SM8521

UART Transmit Data Register (URTT)

Transmit data register URTT is an 8-bit write only

When the transmission operation starts, the content

of this register LSB first is output from P71/TxD pin.

UART Receive Data Register (URTR)

Receive data register URTR is an 8-bit read only

When the receive operation starts, the receive data

LSB first will be moved into the receive data shift

operation is complete, the content of the receive

data shift register is loaded into this receive data

UART Status Register (URTS)

Status register (URTS) is an 8-bit read only register

containing the flags of the UART interface transmit/

receive status.

Bit 7

Bits 7 to 6 : Set ‘0’

Bit 5 : Receiver busy bit (RBSY)

Bit 4 : Overrun error bit (OR)

Bit 3 : Frame error bit (FE)

Bit 2 : Parity error bit (PE)

Bit 1 : Transmit data register empty bit (TDRE)

Bit 0 : Receiver data register full bit (RDRF)

RBSY OR

PE TDRE TDRF

BIT

CONTENT

UART receiver is other than the following.

UART receiver processing incoming data.

BIT

CONTENT

Clear condition

(1) While reading the status register URTS

(2) Hardware reset

Set condition

(1) While overrun error occurs (the next

receive is complete under the bit RDRF

‘1’. ) at receive data

BIT

CONTENT

Clear condition

(1) While reading the status register URTS

(2) Hardware reset

Set condition

(1) While frame error occurs (stop bit =

‘0’

is detected.) at receive data.

BIT

CONTENT

Clear condition

(1) While reading the status register URTS

(2) Hardware reset

Set condition

(1) Parity error occurs at receive data

BIT

CONTENT

Clear condition

(1) While writing to transmit data register

URTT

Set condition

(1) While having finished transmitting

operation.

(2) Hardware reset

BIT

CONTENT

Clear condition

(1) While reading from receive data register

URTR

(2) Hardware reset

Set condition

(1) While receive data is transferring to

receive data register URTR from receive

data shift register.

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