SM8521 datasheet(38/56 Pages) SHARP

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SM8521

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LCV (Display vertical timing register)

Bit 7

Bit 7 : V-blank bit (read only)

Bit 6 : Sets ‘0’.

Bits 5 to 4 : V-line size bits

Bits 4 to 0 : V-blank width bits

NOTE :

V-blank width bit must not be filled with 0000B. Otherwise,

LCDC interrupt can not be effective.

Horizontal display cycle = (shift clock x LCDC/DMA

clock ) x (H-timing + 1)

Shift clock = 40 (at H-dot size = 160),

50 (at H-dot size = 200)

Frame cycle = Horizontal display cycle x (V-line

size + V-blank width)

DMC (DMA control register)

Bit 7

Bit 7 : DMA start bit

Bits 6 to 5 : Set ‘0’.

Bit 4 : Increment y/decrement y bit

(Increment/decrement y-coordinate of source)

Bit 3 : Increment x/decrement x bit

(Increment/decrement x-coordinate of source)

Bits 2 to 1 : Transfer mode bits

Bit 0 : Compound/overwrite bit

BIT

SOURCE

→DESTINATION

VRAM

→VRAM

ROM

→VRAM

VBLNK

VL1

VL0 VBWD3 VBWD2 VBWD1 VBWD0

BIT

STATUS

Non-vertical blank period

Vertical blank period

BIT

STATUS

DMA stops

DMA starts transfering data

BIT

STATUS

Increment y

Decrement y

BIT

STATUS

Increment x

Decrement x

Extend RAM

→VRAM

VRAM

→Extend RAM

BIT

STATUS

Compound mode

Overwrite mode

BIT

VERTICAL LINE SIZE

100

160

200

DMST

INDCY INDCX TRN1 TRN0 COOVr

SM8521 Datasheet(PDF) 38 Page - Sharp Corporation

SM8521 Datasheet(HTML) 38 Page - Sharp Corporation

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