SM8521 datasheet(43/56 Pages) SHARP

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SM8521

- 43 -

In order of Low and High, each 4-bit data is

specified. Each SG0 and SG1 waveform register

stores 4-bit x 32-step data as shown below.

Refer to SG0 and SG1 waveform registers in Fig.

9-3.

The most significant bit of each 4-bit data indicates

positive and negative.

That means, range of each 4-bit data is –8 to +7.

NOTE :

Waveform register read/write is possible only when SG is

disable.

STEP0

STEP2

STEP4

STEP6

STEP8

STEP10

STEP12

STEP14

STEP1

STEP3

STEP5

STEP7

STEP9

STEP11

STEP13

STEP15

STEP16

STEP18

STEP20

STEP22

STEP24

STEP26

STEP28

STEP30

STEP17

STEP19

STEP21

STEP23

STEP25

STEP27

STEP29

STEP31

Fig. 20

Sound Waveform Register

+2.5 V

+5.0 V

D/A output level

Time

Rump-up period

Rump-down period

Fig. 21

Example of D/A Output

NOTES :

• Mute level of the D/A should be created by software.

• Attenuate not to exceed capacity of D/A output level (0-5 V) by software.

• To avoid pop-noise, make rump-up and down period by software.

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