SM8521 datasheet(32/56 Pages) SHARP

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SM8521

- 32 -

CLOCK TIMER REGISTER

CLKT (Clock timer register)

Bit 7

Bit 7 : Run/reset

Bit 6 : Minute/second

Bits 5 to 0 : Value of counter (read only)

Watchdog Timer Register (WDT)

PRS2 (Prescaler 2)

Prescaler PRS2 generates the count clock to

watchdog timer counter WDT.

The following conditions are to clear all bits of

prescaler PRS2.

• When hardware reset.

• When watchdog timer counter WDT stopped.

• When counter WDT is cleared by writing ‘1’ to

the bit WDTCR (bit 3 : WDTC).

Prescaler PRS2 divides the frequency derived from

input clock fc10 (204.8 µs : main-clock = 10 MHz),

then fc11-fc15 are output.

WDT (Watchdog timer counter register)

Watchdog timer counter WDT is an 8-bit read only

WDTC (Watchdog timer control register)

Watchdog timer control WDTC is an 8-bit read only

counter clear designation, and selects the count

clock.

Bit 7

Bit 7 : Watchdog timer start/stop bit (WDTST)

Bit 6 : Operation select while watchdog timer overflow

(WDTRN)

Bits 5 to 4 : set ‘0’.

Bit 3 : Counter clear bit (WDTCR) [write only bit]

Bits 2 to 0 : Watchdog timer counter clock selection

bits (WCNT2-WCNT0)

BIT

COUNT CLOCK

000

fc12 (819 µs∗1)

001

fc13 (1.639 ms∗1)

010

fc14 (3.278 ms∗1)

011

fc15 (6.578 ms∗1)

100

fx5 (0.976 ms∗2)

101

fx6 (1.95 ms∗2)

110

fx7 (3.90 ms∗2)

111

fx8 (7.81 ms∗2)

WDTST WDTRN

WDTCR WCNT2 WCNT1 WCNT0

1/2 1/2 1/2 1/2 1/2

fc11 fc12 fc13 fc14 fc15

PRS2 fc2

BIT

CONTENT

Timer stop [WDT is cleared.]

Timer start

BIT

CONTENT

Hardware reset

Non-maskable interrupt

BIT

CONTENT

No clear

Only in writing operation, WDT is cleared.

BIT

STATUS

1 second

1 minute

BIT

STATUS

Counter reset

Run

∗1 The value in ( ) is the period when main-clock is

10 MHz.

∗2 The value in ( ) is the period when sub-clock is

32.768 kHz.

SM8521 Datasheet(PDF) 32 Page - Sharp Corporation

SM8521 Datasheet(HTML) 32 Page - Sharp Corporation

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