5 Pin Configuration and Functions

1

15

14

13

12

11

10

9

8

PGND

7

6

5

3

2

SW

BOOT

16

PGND

VIN

AGND

EN

MSEL

PG

VIN

VCC

4

PGND

Figure 5-1. RZR Package 16-Pin VQFN-HR Top

View

11

12

13

14

15

1

2

3

5

6

7

9

10

SW

VCC

16

PGND

VIN

PG

MSEL

EN

AGND

VIN

BOOT

4

PGND

8

PGND

Figure 5-2. RZR Package 16-Pin VQFN-HR Bottom

View

Table 5-1. Pin Functions

NO.

NAME

TYPE(1)

DESCRIPTION

2

AGND

G

Analog ground return and reference for the internal control circuits.

5

BOOT

I/O

Supply for the internal high-side MOSFET gate driver (boost terminal). Connect the bootstrap

capacitor from this pin to SW node.

1

EN

I

Enable pin. The enable pin turns the DC/DC switching converter on or off. Floating EN pin before

start-up disables the converter. The recommended maximum voltage applied to the EN pin is 5.5 V.

TI does not recommend connecting the EN pin to VIN pin directly.

14

FB

I

Output voltage feedback input. A resistor divider from the output voltage to GOSNS (tapped to FB

pin) sets the output voltage. Connect the FB divider to the output voltage near the load.

13

GOSNS

I

Negative input of the differential remote sense circuit. Connect to a ground sense point near the

load.

12

ILIM

I

Current limit setting pin. Connect a resistor to AGND to set the current limit trip point. TI

recommends a ±1% tolerance resistor. See Section 7.3.10 for details on OCL setting.

11

MSEL

I

Multi-function select pin. A resistor from the MSEL pin to AGND selects between forced continuous-

conduction mode (FCCM) or skip-mode operation, the operating frequency, and the PWM ramp

setting. A ±1% tolerance resistor is required. See Table 7-1 for details.

10

PG

O

Open-drain power-good status signal. Connect an external pullup resistor to a voltage source.

When the FB voltage moves outside the specified limits, PG goes low after the specified delay.

4, 8, 16

PGND

G

Ground return for the power stage. This pin is internally connected to the source of the low-side

MOSFET. Place as many vias as possible beneath the PGND pins and as close as possible to the

PGND pins. This minimizes parasitic impedance and also lowers thermal resistance.

15

SS

O

Connect a capacitor to AGND to set the SS time. A minimum 10-nF capacitor is required for this pin

to avoid overshoot during the charge of soft-start capacitor.

6

SW

O

Output switching terminal of the power converter. Connect this pin to the output inductor.

7

VCC

P

Internal 3-V LDO output. A 3.3-V or 5-V external bias can be connected to this pin to save the

power losses on the internal LDO. The voltage source on this pin powers both the internal circuitry

and gate driver. Bypass with a 1-μF, > 6.3-V rating, ceramic capacitor from VCC pin to PGND. Place

this capacitor as close to the VCC and PGND pins as possible.

3, 9

VIN

P

Power-supply input pins for both the power stage MOSFETs and the internal LDO. Place the

decoupling input capacitors from VIN pins to PGND pins as close as possible. A capacitor from

each VIN to PGND close to IC is required.

(1)

I = Input, O = Output, P = Supply, G = Ground

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TPS54KB20

SLVSGP3 – MAY 2023

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