Equation 20 and Equation 21 calculate the minimum capacitance to meet the transient response requirement of

TBD with a TBD step. These equations calculate the necessary output capacitance to hold the output voltage

steady while the inductor current ramps up or ramps down after a load step.

TBD

(20)

TBD

(21)

The output capacitance needed to meet the overshoot requirement is the highest value, so this sets the

required minimum output capacitance for this example. Stability requirements can also limit the maximum output

capacitance. Equation 22 calculates the recommended maximum output capacitance. This calculation keeps

the LC double pole above 1/100th the fSW. Using more output capacitance, is possible, but the stability must

be checked through a bode plot or transient response measurement. The selected output capacitance is TBD

ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to DC and AC bias

effects. The selected capacitors derate to TBD their nominal value giving an effective total capacitance of TBD

879.5 μF. This effective capacitance meets the minimum and maximum requirements.

TBD

(22)

This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If

using non ceramic capacitors, as a starting point, the ESR must be below the values calculated in Equation 23 to

meet the ripple requirement and Equation 24 to meet the transient requirement. For more accurate calculations

or if using mixed output capacitors, the impedance of the output capacitors must be used to determine if the

ripple and transient requirements can be met.

TBD

(23)

TBD

(24)

8.2.2.6 Choose the Input Capacitors (CIN)

The device requires input bypass capacitors between both pairs of VIN and PGND pins to bypass the power-

stage. The bypass capacitors must be placed as close as possible to the pins of the IC as the layout allows.

At least 20-µF nominal of ceramic capacitance and two high frequency ceramic bypass capacitors are required.

A 0.1-μF to 1-μF capacitor must be placed as close as possible to both VIN pins 3 and 9 on the same side of

the board of the device to provide the required high frequency bypass, to reduce the high frequency overshoot

and undershoot on across the power-stage on the VIN and SW pins. At least 1 μF of bypass capacitance

is recommended as close as possible to each VIN pin to minimize the input voltage ripple. The ceramic

capacitors must be a high-quality dielectric of X6S or better for their high capacitance-to-volume ratio and

stable characteristics across temperature. In addition to this, more bulk capacitance can be needed on the input

depending on the application to minimize variations on the input voltage during transient conditions.

The input capacitance required to meet a specific input ripple target can be calculated with Equation 25. A

recommended target input voltage ripple is 5% the minimum input voltage, TBD mV in this example. The

calculated input capacitance is TBD 20.2 μF. This example meets these two requirements with TBD × TBD-µF

ceramic capacitors.

TBD

(25)

The capacitor must also have an RMS current rating greater than the maximum input RMS current in the

application. The input RMS current the input capacitors must support is calculated by Equation 26 and is TBD A

9.874 A in this example. The ceramic input capacitors have a current rating greater than this value.

TBD

(26)

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current, TI

recommends the selection process in How to select input capacitors for a buck converter.

www.ti.com

TPS54KB20

SLVSGP3 – MAY 2023

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