8.4 Layout

8.4.1 Layout Guidelines

Before beginning a design using the device, consider the following:

• VIN, PGND, and SW traces must be as wide as possible to reduce trace impedance and improve heat

dissipation.

• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side

of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid

ground inner plane.

• Placement of the VIN decoupling capacitors are important for the power MOSFET robustness. A 1-μF/25-V/

0402 ceramic high-frequency bypass capacitor on each VIN pin (pin 3 and 9) is required, connected to the

adjacent PGND pins (pin 4 and 8 respectively). Place the remaining ceramic input capacitance next to these

high frequency bypass capacitors. The remaining input capacitance can be placed on the other side of the

board, but use as many vias as possible to minimize impedance between the capacitors and the pins of the

IC.

• Place eight vias below the PGND pins (pins 4, 8, and 16) and as many vias as possible near the PGND pins

(pin 4 and 8). This action minimizes parasitic impedance and also lowers thermal resistance.

• Use vias near both VIN pins and provide a low impedance connection between them through an internal

layer. A via can also be placed below each of the VIN pins.

• Place the VCC decoupling capacitor as close as possible to the device, with a short return to PGND pin

8. Ensure the VCC decoupling loop is small and use traces with a width of 12 mil or wider to route the

connection.

• Place the BOOT capacitor as close as possible to the BOOT and SW pins. Use traces with a width of 12 mil

or wider to route the connection.

• The PCB trace, which connects the SW pin and high-voltage side of the inductor, is defined as switch node.

The switch node must be as short and wide as possible.

• Always place the feedback resistors near the device to minimize the FB trace distance, no matter single-end

sensing or remote sensing.

– For remote sensing, the connections from the FB voltage divider resistors to the remote location must be

a differential pair of PCB traces, and must implement Kelvin sensing across a bypass capacitor of 0.1 μF

or higher. The ground connection of the remote sensing signal must be connected to GOSNS pin. The

VOUT connection of the remote sensing signal must be connected to the feedback resistor divider with the

bottom feedback resistor terminated to the GOSNS pin. To maintain stable output voltage and minimize

the ripple, the pair of remote sensing lines must stay away from any noise sources such as inductor and

SW nodes, or high frequency clock lines. TI recommends to shield the pair of remote sensing lines with

ground planes above and below.

– For single-end sensing, connect the top feedback resistor between the FB pin and the output voltage to a

high-frequency local output bypass capacitor of 0.1 μF or higher, and short GOSNS to AGND with a short

trace.

• Connect the AGND pin (pin 2) to the PGND pad (pin 16) beneath the device.

• Return the MSEL resistor, ILIM resistor, and SS capacitor to a quiet AGND island.

• Avoid routing the PG signal and any other noisy signals in the application near noise sensitive signals, such

as ILIM, FB and GOSNS to limit coupling.

• See Layout Example for the layout recommendation.

www.ti.com

TPS54KB20

SLVSGP3 – MAY 2023

Copyright © 2023 Texas Instruments Incorporated

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