7.3 Feature Description

7.3.1 Internal VCC LDO And Using External Bias On the VCC Pin

The TPS54KB2x has an internal 3.0-V LDO featuring input from VIN and output to VCC. When the EN voltage

rises above the enable threshold (VEN(R)), the internal LDO is enabled and starts regulating output voltage on the

VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry and also provides the supply

voltage for the gate drivers.

Bypass the VCC pin with a 1-µF, at least 6.3-V rating ceramic capacitor. An external bias that is above the output

voltage of the internal LDO can override the internal LDO. This enhances the efficiency of the converter because

the VCC current now runs off this external bias instead of the internal linear regulator. An external bias of 5.0

V can be used to provide additional efficiency enhancement by reducing the RDSON of the integrated power

MOSFETs.

The VCC UVLO circuit monitors the VCC pin voltage and disables the whole converter when VCC falls below the

VCC UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of

the device.

Considerations when using an external bias on the VCC pin are as follows:

• When the external bias is applied on the VCC pin early enough (for example, before EN signal comes in), the

internal LDO pass device is always off and the internal analog circuits will have a stable power supply rail at

their power enable.

• (Not recommended) When the external bias is applied on the VCC pin late (for example, after EN signal

comes in), any power-up and power-down sequencing can be applied as long as there is no excess current

pulled out of the VCC pin. With this sequence, be cautious of external discharge paths on the VCC pin which

can pull a current higher than the current limit of the internal VCC LDO. A load exceeding the current limit of

the internal VCC LDO can potentially pull the VCC voltage low and turn off the VCC LDO through its UVLO,

thereby shutting down the converter output.

• A good power-up sequence is when at least one of VIN UVLO rising threshold or EN rising threshold is

satisfied later than VCC UVLO rising threshold. For example, a practical power-up sequence is: VIN applied

first, then the external bias applied, and then EN signal goes high.

7.3.2 Enable

When the EN pin voltage rises above the enable threshold voltage (VEN(R)) and VIN rises above the VIN UVLO

rising threshold, the device enters its internal power-up sequence. The EN to start of switching delay is specified

in the STARTUP section of the Electrical Characteristics table.

The EN pin has an internal filter to avoid unexpected ON or OFF due to small glitches. The time constant of this

RC filter is 2 µs. For example, when applying 3.3-V voltage source on the EN pin that jumps from 0 V to 3.3

V with an ideal rising edge, the internal EN signal will reach 2.1 V after 2 µs, which is 63.2% of applied 3.3-V

voltage level.

An internal pulldown resistor is implemented between the EN pin and AGND pin. With this pulldown resistor,

floating the EN pin before start-up keeps the device in the disabled state. A resistor divider to the EN pin can

be used to increase the input voltage the device begins its start-up sequence. The internal pulldown resistor

must be accounted for when using an external resistor divider. To reduce impact to the EN rising and falling

threshold, this internal pulldown resistor is 1 MΩ. During nominal operation when the power stage switches, this

large internal pulldown resistor may not have enough noise immunity to hold EN pin low for the device to enter

the disabled state.

The recommended operating condition for the EN pin is a maximum of 5.5 V. Do not connect the EN pin to the

VIN pin directly if VIN can exceed 5.5 V.

TPS54KB20

SLVSGP3 – MAY 2023

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