EB632 datasheet(21/112 Pages) FREESCALE

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Clock System

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

6.5

CLKIN-to-CLKOUT Delay Change

For the 2K42A mask set, the CLKIN-to-CLKOUT delay is a function of frequency. For the 2K87M mask set, the

CLKIN

-to-CLKOUT delay is a not a function of frequency. Therefore, the two versions cannot be used together in a

DLL-disabled system.

6.6

Enabling the DLL

For the 2K42A, system erratum QSIU14 requires that the MSC8101 use only DLL-disabled mode and a zero-delay

buffer. To use the MSC8103 mask set 2K87M in such a design with the DLL-enabled, the zero-delay buffer must

either be placed in PLL-bypass mode or replaced.

6.7

Disabling the DLL

The 2K87M AC timing specification listed in the MSC8103 Technical Data sheet is for DLL-enabled mode only

and is therefore referenced to DLLIN. For 2K87M clock modes 5, 6, 46, and 57 only, apply the following offsets to

accommodate for the fact that the signal is referenced to CLKOUT instead of DLLIN:

•

For SIU outputs, add 400 ps.

•

For DMA outputs, add 400 ps to specification 76.

•

For SIU inputs, subtract 400 ps.

•

For DMA inputs, subtract 400 ps from specifications 72–75.

6.8

Clock Frequency Changes

lists the maximum clock frequencies for each mask set.

Note:

Refer to MSC8103 Technical Data for details on all frequency ranges and limitations.

Table 15. Maximum Clock Frequencies for Each Mask Set

Clock

2K42A Maximum Frequency

2K87M Maximum Frequency

Input Clock (CLKIN)

68.75 MHz

75 MHz

Internal Bus Clock (BCLK)

68.75 MHz

100 MHz

Output Clock (CLKOUT)

68.75 MHz

100 MHz

SCC Clock (SCLK)

68.75 MHz

100 MHz

CPM Clock (CPMCLK)

137.5 MHz

200 MHz

SC140 Core Clock (DSPCLK)

275 MHz

300 MHz

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