EB632 datasheet(33/112 Pages) FREESCALE

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HDI16

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

HREQ

HREQ Status

HREQ indicates the status of the external transmit and

receive request output signals (HTRQ and HRRQ) if HDRQ

is set. If HDRQ is cleared, it indicates the status of the

external host request output signal (HREQ). The HREQ bit

can be set under either or both of two conditions: the

Receive Word Registers (RX[0–3]) are full or the Transmit

Word Registers (TX[0–3]) are empty. These conditions are

indicated by the ISR RXDF and TXDE status bits,

respectively. If the interrupt source has been enabled by the

associated request enable bit in the ICR, HREQ is set if one

or more of the two enabled interrupt sources is set.

If HDRQ is cleared:

No host processor interrupts requested.

Interrupt requested.

If HDRQ is set:

No host processor interrupts requested (HTRQ and

HRRQ cleared).

Interrupt requested (HTRQ or HRRQ set).

HF[4–7]

9–12

Host Flags 4–7

Indicates the state of host flags 4

–7 in the HCR on the core

side. Only the SC140 core can change HF[4

–7].

TRDY

TRDY Status

Indicates whether the Transmit Word Registers TX[0

–3] and

the HORX FIFO are empty. TRDY is set if TXDE is set and

HRFNE is cleared. If TRDY is set, the data that the host

processor writes to TX[0

–3] is immediately transferred to the

core side of the HDI16 and can be read by the SC140 core.

This feature has many applications. For example, if the host

processor issues a host command that causes the SC140

core to read HORX, the host processor can be certain that

the data it just transferred to the HDI16 is the same data

received by the SC140 core.

0TX[0

–3] and the HORX FIFO are not empty.

TX[0–3] and the HORX FIFO are empty.

TXDE

Transmit Data Empty

Indicates whether the Transmit Word Registers (TX[0

–3])

are empty and can be written by the host processor. TXDE is

set when the contents of the TX[0

–3] registers are

transferred to the HORX register. TXDE is cleared when the

host processor writes to the transmit data registers (TX) and

the HORX FIFO is full. The host processor sets TXDE using

the initialize function. TXDE can assert the external

HREQ/HTRQ signal if the TREQ bit is set. Regardless of

whether the TXDE interrupt is enabled, TXDE indicates

whether the TX registers are full and data can be latched in

so that the host processor can use polling techniques.

The TX registers are not empty.

The TX registers are empty and can be written by the

host processor.

RXDF

Receive Data Full

Indicates whether the Receive Word Registers (RX[0

–3])

contain data from the SC140 core and can be read by the

host processor. RXDF is set when the HOTX is transferred

to the RX[0

–3] registers. RXDF is cleared when the host

processor reads the receive data registers (RX) at the last

address and the HOTX FIFO is empty. The host processor

can clear RXDF using the initialize function. RXDF can be

used to assert the external HREQ/HRRQ signal if RREQ is

set.

Regardless of whether the RXDF interrupt is enabled, RXDF

indicates whether the RX registers are full and data can be

latched out, so that the host processor can use polling

techniques.

The RX registers are not full.

The RX registers are full and can be read by the host

processor.

Note:

A status bit is set when there are a number of empty/full bytes more than the status bit indicates. For example, if there are 32

empty bytes, all three relevant status bits (TXDE32, TXDE16, and TXDE) are set.

Table 30. 2K87M Mask Set ISR Bit Descriptions (Continued)

Name

Description

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