EB632 datasheet(15/112 Pages) FREESCALE

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Clock System

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

6.1.2 Mask Set 2K87M Clock Scheme

Six bit values map the MSC8101 clocks to one of the valid configuration mode options. Each option determines the

CLKIN

, SC140 core, system bus, SCC clock, CPM, and CLKOUT frequencies. The six bit values are derived from

three dedicated input pins (MODCK[1–3]) and three bits from the hard reset configuration word (MODCK_H). To

configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140 core, SCC

clocks, CPM parallel I/O ports, and system buses, the MODCK[1–3] pins are sampled and combined with the

MODCK_H values when the internal power-on reset (internal PORESET) is deasserted. Clock configuration

changes only when the internal PORESET signal is deasserted.

The following factors are configured:

•

SPLL pre-division factor (SPLL PDF)

•

SPLL multiplication factor (SPLL MF)

•

Bus post-division factor (Bus DF)

•

CPM division factor (CPM DF)

•

Core division factor (Core DF)

•

CPLL pre-division factor (CPLL PDF)

•

CPLL multiplication factor (CPLL MF)

Figure 5 shows the functional block diagram for the 2K87M mask set. The 2K87M mask set contains an internal

system phase-lock loop (SPLL) and a core phase-lock loop (CPLL).

Figure 5. MSC8103 Clock Functional Block Diagram for 2K87M Mask Set

System Bus Clock

CPM Clock

CLKIN

SCC Clock

BRG Clock

CLKOUT

SC140

Bus

SCC

SPLL

PDF

SPLL

BRG

CKO

CPM

DLL

Note:

SPLL PDF, SPLL MF, Core DF, CPLL PDF, CPLLMF, and CPM DF are determined by the clock configuration

mode; Bus DF = CKO DF and is determined by the clock configuration mode; SCC DF is always 4; BRG DF is set

by the System Clock Control Register (SCCR) and is 4, 16 (default), 64, or 256.

Key:

SPLL PDF: System PLL Pre-Division Factor

SPLL MF: System PLL Multiplication Factor

DLL: Delay Lock Loop

Bus DF: Bus Division Factor

SCC DF: SCC Division Factor

CPM DF: CPM Division Factor

BRG DF: Baud Rate Generator Division Factor

CKO DF: CLKOUT Division Factor

Core DF: Core Division Factor

CPLL PDF: Core PLL Pre-Division Factor

CPLL MF: Core PLL Multiplication Factor

DLLIN

Core

CPLL

PDF

CPLL

Core Clock

Core PLL

System PLL

EB632 Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc

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