EB632 datasheet(30/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

HDI16

Table 25 shows the effects of the INIT command in relation to the values of TREQ and RREQ.

Table 26 and Table 27 summarize the effect of RREQ and TREQ on the HREQ and HRRQ signals.

Table 28 shows the valid HM values and their meaning.

9.2

Interface Status Register (ISR) Changes

The following sections lists the ICR layout and definitions for the 2K42A and 2K87M mask sets.

Table 25. Effects of the INIT Command

TREQ

RREQ

After INIT Execution

Transfer Direction

Initialized

INIT = 0

None

INIT = 0; ISR[RXDF] = 0; HSR[HTFE/HTFNF] = 1

Core to host

INIT = 0; ISR[TXDE] = 1; HSR[HRFF/HRFNE] = 0

Host to core

INIT = 0; ISR[RXDF] = 0; HSR[HTFE/HTFNF] = 1;

ISR[TXDE] = 1; HSR[HRFF/HRFNE] = 0

Host to/from core

Table 26. TREQ and RREQ Modes (HDRQ = 0) in Non-DMA Mode (HICR=1)

TREQ

RREQ

HREQ Signal

No interrupts (polling)

ISR[RXDF] request (interrupt)

ISR[TXDE] request (interrupt)

ISR[RXDF] and ISR[TXDE] request (interrupts)

Table 27. TREQ and RREQ Modes (HDRQ = 1) in Non-DMA Mode (HICR=1)

TREQ

RREQ

HTRQ Signal

HRRQ Signal

No interrupts (polling)

ISR[RXDF] request (interrupt)

ISR[TXDE] request (interrupt)

No interrupts (polling)

ISR[TXDE] request (interrupt)

ISR[RXDF] request (interrupt)

Table 28. HM Host DMA Mode Values (HICR=1)

Mode

DMA Mode

Non-DMA Mode

16-bit words

64-bit words. Last read/write (trigger) address: 0x4

32-bit words

48-bit words. Last read/write (trigger) address: 0x5

48-bit words

32-bit words. Last read/write (trigger) address: 0x6

64-bit words

16-bit words. Last read/write (trigger) address: 0x7

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