EB632 datasheet(76/112 Pages) FREESCALE

76 / 112 page

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Errata

SC7

Change of Flow May Cause Incorrect Trace-Buffer Data

Date Added: 2/19/2002

Description: When the EOnCE module is programmed for tracing events of change of flow

(TCHOF) and interrupts (TINT), the Trace Buffer is updated on every event by the source and

destination addresses. In the event of a change of flow (CHOF) to another CHOF with an interrupt

request in between, the Trace Buffer is updated with additional data. The additional data is incor-

rect and is not needed for the trace.

Workaround: Perform post-processing after reading the Trace Buffer. Search in the data for a

source address with its destination listed before it. Delete the source and the previous data.

System Number: 7794

Fix Plan: TBD

0K40A

1K42A

2K42A

2K87M

SC8

Debug Exception Request From JTAG is Not Accepted During Core Freeze

Date Added: 5/21/2002

Description: JTAG debug exception request is not accepted by the core during freeze. If the re-

quest is asserted and deasserted during a core freeze, the request is discarded.

Workaround: Assert Debug request from JTAG. When entering the exception routine, use soft-

ware to assert an external pin (one of the EE pins, for example) to signal that the Exception Ser-

vice Routine was executed. After that, a new JTAG instruction can be written.

Fix Plan: TBD

0K40A

1K42A

2K42A

2K87M

SC9

EE Pins Do Not Enable Different EOnCE Modules During Core Freeze

Date Added: 5/21/2002

Description: If EE pins are asserted to enable events in the EOnCE modules during a core freeze

and the request is deasserted during the same core freeze, the event is not enabled.

Workaround: Poll core status from JTAG. After the core is not in a freeze state, assert the EE

pin(s) for at least three cycles.

Fix Plan: TBD

0K40A

1K42A

2K42A

2K87M

CPM94

FCC RTS Signal Not Asserted Correctly

Date Added: 2/25/2003

Description: At the beginning of an HDLC frame transmission which is preceded by more than

one opening flag, RTS will not be asserted if CTS is negated. This may cause a deadlock if the

modem waits for the assertion of RTS before asserting CTS.

Workaround: Implement one of the following:

Transmit no flags between or before frames.

Clear FPSMR[NOF] bit. Set GFMR[RTSM]=1 to ensure RTS/ is asserted when

FCC is enabled. However no hand shaking activities with the modem will occur for

all the proceeding frames.

Fix Plan: TBD

2K87M

CPM96

ATM Performance Monitoring with AAL1 CES

Date Added: 2/25/2003

Description: ATM Performance Monitoring with AAL1 CES Data in DPRAM is corrupted

when performance monitoring is enabled in the receiver.

Workaround: Impelement one of the following:

Disable Receive Performance Monitoring RCT[PMT]=0.

Use microcode patch available from Freescale.

Fix Plan: TBD

0K40A

1K42A

2K42A

2K87M

Table 50. 2K87M Errata

Errata

Number

Errata Description

Applies

to Mask

EB632 Datasheet(PDF) 76 Page - Freescale Semiconductor, Inc

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