EB632 datasheet(9/112 Pages) FREESCALE

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Boot

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

5Boot

The 2K42A mask set does not support a serial boot mode. The 2K87M mask set supports a serial boot mode with a

reduced reset configuration. The following sections describe the serial boot mode operations.

5.1

Boot Mode Definition Changes

The boot modes for mask set 2K42A are defined by the values of BTM[0–1] when sampled on the rising edge of

PORESET

, as follows:

The boot modes for mask set 2K87M are defined by the values of BTM[0–1] when sampled on the rising edge of

PORESET

, as follows:

5.2

Serial EPROM Boot Procedure

The MSC8103 core programs the I2C registers and parameter RAM and prepares buffers and buffer descriptors

(BDs) for the boot loading process. The MSC8103 I

2C interface is programmed as the master, and it accesses the

slave address 0b1010111 to read the boot source code. Booting the MSC8103 through the serial EPROM is useful

for systems in which the MSC8103s are connected only through serial interfaces, such as TDM, Ethernet, ATM,

and so forth.

Note:

The bootloader supports access to serial EPROMS with a user-defined device address and 2-byte address

specifications.

5.3

Software Watchdog Handling

The software watchdog timer can be enabled by clearing the SWDIS bit as part of the reduced reset configuration

process. In serial boot mode, if the SWDIS bit is cleared, the bootloader program periodically executes a special

service sequence to prevent the time-out of its counter and the assertion of a hardware reset during the bootloading

process. For details on the software watchdog, refer to Section 4.2.5, Software Watchdog Timer, and Section 4.3,

SIU Programming Model in the MSC8103 Reference Manual.

BTM0

BTM1

Boot Source

External memory

HDI16

Reserved

BTM0

BTM1

Boot Source

External memory

HDI16

Serial interface

Reserved

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