EB632 datasheet(22/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Memory Map

The 2K87M mask adds the IMMMR to the memory map. The 2K87M memory map for Bank1 of the QBus is

shown in Table 16.

ORx in UPM Mode

In UPM mode, the 2K42A mask uses the previously undefined bit 27 in the ORx to add a wait state to the memory

cycle when set. In the 2K87M mask set, this bit is undefined.

9HDI16

The 2K87M mask set defines additional bits in the Interface Control Register (ICR) and Interface Status Register

(ISR) to support HDI16 bursts of various sizes. This affects the conditions used to assert or deassert the HREQ

signal. The following sections compare the register layouts for the two mask sets and indicate the changes to the

logic used to assert the HREQ signal.

9.1

Interface Control Register (ICR) Changes

The following sections list the ICR layout and definitions for the 2K42A and 2K87M mask sets.

9.1.1 2K42A Mask Set ICR Definitions

Table 16. Mask Set 2K87M QBus Memory Map—Bank1

SC140 Core

Internal Address

Mnemonic

Name

Size

Boot ROM

0000–07FF

BOOTROM

MSC8103 boot ROM

2 KB

0800–FFBF

Reserved

Leave unchanged for future compatibility

63 KB – 64 bytes

FFC0

IMMMR

Internal Memory Map Mirror Register

32 bits

FFC4–FFFF

Reserved

Leave unchanged for future compatibility

60 bytes

ICR

Mask Set 2K42A Interface Control Register (DMA = 0, HICR = 1)

0x0

Bit

—

HF0

HF1

—

INIT

HF2

HF3 HDRQ TREQ RREQ

Type

R/W

Reset

See Table 18 on page 25

ICR

Mask Set 2K42A Interface Control Register (DMA = 1, HICR = 1)

0x0

Bit

—

HF0

HF1

—

INIT

HF2

HF3

—

TREQ RREQ

Type

R/W

Reset

See Table 18 on page 25

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