EB632 datasheet(56/112 Pages) FREESCALE

56 / 112 page

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Errata

15 Errata

Table 48 lists the functional errata that the 2K87M mask removes and the current 2K87M mask set errata. Always

refer to the Freescale website listed on the back page of this document for a current list of device errata.

Table 47.

2K87M Mask Set New Command Descriptions

Command

Description

INIT MCC RX

AND TX

PARAMS —

ONE

CHANNEL

Initializes the receive and transmit parameters of the peripheral controller. Differs from INIT RX AND TX PARAMS in that,

for the MCCs, issuing INIT RX AND TX PARAMS initializes 32 consecutive channels beginning with the channel number

specified in CPCR[MCN]. However, issuing INIT MCC RX AND TX—ONE CHANNEL initializes only the channel in the

command.

INIT MCC RX

PARAMS—

ONE

CHANNEL

Initializes MCC receive parameters for only a single channel according to MCC channel number field.

INIT TX

PARAMS—

ONE

CHANNEL

Initializes MCC transmit parameters for only a single channel according to MCC channel number field.

MCC RESET

Provides a hard reset to the MCC FIFOs. To use this command, software should execute the following sequence:

Disable the TDM by clearing the appropriate enable bit in SIxGMR[4-7].

Issue the MCC RESET command.

Issue the INIT RX AND TX command.

Reprogram the specific MCC channel, global parameters, and any BDs that need to be updated.

Set the appropriate enable bit in SIxGMR[4–7].

Table 48. Errata Resolved in Mask Set 2K87M

Errata

Number

Errata Description

Applies

to Mask

SIU1

Wrong Timer Advancement on RCCR

Date Added: 5/30/2000:

Description: PQ2 treats the RCCR[TIMEP] value (UC timer) differently then QUICC. In

QUICC the timer advanced (N+1)*1024 cycles and in MSC8101 and MPC826X the timer ad-

vances N*1024 cycles.

Workaround: None

System Number: 1399

0K40A

1K42A

2K42A

SIU4

Incorrect Masking of MCP

Date Added: 5/30/2000:

Description: MCP (Machine Check Interrupt) due to data errors (parity / ECC) is masked by the

SWRI bit in SYPCR.

Workaround: Clear the SWRI bit in SYPCR to get data errors indication.

System Number: 3695

0K40A

1K42A

2K42A

EB632 Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc

EB632 Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL