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EB632 Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

Part # EB632
Description  Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M)
PDF  112 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

EB632 Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2
46
Freescale Semiconductor
CPM
The RCF can perform single bit error correction on the header. If multiple bit errors are found in the HEC, the cell
is discarded. If the single bit error correction mode is not enabled (TCMODE[SBC] = 1), the cell is also discarded
when a single bit error is found in the header.
When the cell delineation state machine is in the SYNCH state, the HEC verification state machine (see Figure 17)
implements the correction algorithm. This state machine ensures that a single cell header is corrected at a time. If
consecutive cells are detected with single bit errors in their headers, only the first cell error is corrected and the rest
are discarded. This state machine reduces the delivery of cells with headers containing errors under bursty error
conditions.
The RCF can also perform idle/unassigned cell filtering. Both features are programmable (TCMODE[CF]). Cells
that are detected to be idle/unassigned are discarded, that is, not forwarded to the UTOPIA interface Rx FIFO.
14.4.6 Receive ATM 2-Cell FIFO
The receive FIFO provides FIFO management and an interface to the UTOPIA receive cell interface. The receive
FIFO can hold 2 ATM cells, thereby providing the cell rate decoupling function between the transmission system
physical layer and the ATM layer. FIFO management includes filling the FIFO, indicating to the UTOPIA interface
that it contains cells, maintaining the FIFO read and write pointers, and detecting FIFO overrun (TCER[OR])
conditions.
14.4.7 Transmit ATM Cell Functions
The transmit ATM cell functions block (TCF) performs the ATM cell payload scrambling and is responsible for the
HEC generation and the idle/unassigned cell generation. The TCF scrambles (programmable by the user) the cell
payload using the self-synchronizing scrambler with polynomial x
43 + 1. The HEC is generated using the
polynomial x8 + x2 + x + 1. The coset polynomial x6 +x4 + x2 + 1 is added (modulo 2) (programmable by the user)
to the calculated HEC octet. The result overwrites the HEC octet on the transmitted cell. When the transmit FIFO is
empty, the TCF inserts idle/unassigned cells (counted in ICC). The TCF accumulates the number of transmitted
assigned cells in a counter (TCC).
14.4.8 Transmit ATM 2-Cell FIFO
The transmit FIFO provides FIFO management and an interface to the UTOPIA transmit interface. The FIFO
provides the cell rate decoupling between the transmission system physical layer and the ATM layer.
Figure 17. HEC: Receiver Modes of Operation
Detection
Correction
Multi-bit error
Mode
Mode
detected
(Cell discarded)
No error detected
(correction)
Single-bit error detected
Error detected
(Cell discarded)
No error detected
(No action)



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