EB632 datasheet(18/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Clock System

6.3

System Clock Control Register (SCCR)

The 2K87M mask set adds a new field (CLKODIS) to the SCCR. The functionality of the common field (DFBRG)

is the same. Figure 8 shows the register layout and Table 12 lists the bit descriptions.

SPLLMF

20–23

Configuration

Pins

Unaffected

SPLL Multiplication Factor

0101

SPLL MF = 10

0110

SPLL MF = 12

0111

SPLL MF = 14

1000

SPLL MF = 16

1001

SPLL MF = 18

1010

SPLL MF = 20

1011

SPLL MF = 22

1100

SPLL MF = 24

1101

SPLL MF = 26

1110

SPLL MF = 28

1111

SPLL MF = 30

All other combinations not used

—

——

Reserved

DLLDIS

Configuration

Pins

Unaffected

DLL Disable

DLL operation is enabled

DLL is disabled

—

26–27

——

Reserved

COREDF

28–31

Configuration

Pins

Unaffected

Core Division Factor

0000

CORE DF = 1

0001

CORE DF = 2

0010

CORE DF = 3

0011

CORE DF = 4

0100

CORE DF = 5

0101

CORE DF = 6

All other combinations not used.

Bit

—

Type

Reserved

Reset

—

Bit

1617

192021

232425

272829

—

CLKODIS

—DFBRG

Type

Reserved

R/W

Reserved

R/W

Reset

—

Figure 8. System Clock Control Register (SCCR)—0x10C80

Table 12. SCCR Bit Descriptions

Name

Bit No.

Defaults

Description

Settings

PORESET

Hard Reset

—

0–26

—

Reserved. Write to 0 fro future compatibility.

CLKODIS

0Unaffected

CLKOUT Disable

Disables the CLKOUT signal. The value of

CLKOUT when disabled is indeterminate (can be 1

or 0).

CLKOUT enabled (default)

CLKOUT disabled

Note: This bit is reserved in mask set

2K42A.

Table 11. 2K87M Mask Set SCMR Field Descriptions (Continued)

Name

Bit No.

Defaults

Description

Settings

PORESET

Hard Reset

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