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EB632 Datasheet(PDF) 19 Page - Freescale Semiconductor, Inc

Part # EB632
Description  Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M)
PDF  112 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

EB632 Datasheet(HTML) 19 Page - Freescale Semiconductor, Inc

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Clock System
Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2
Freescale Semiconductor
19
6.4
Clock Mode Changes
6.4.1 2K42A Mask Set Clock Configuration Modes
The MSC8101 2K42A mask set supports the following valid clock modes:
6.4.2 2K87M Mask Set Clock Modes
The MSC8103 2K87M mask set supports the clock modes listed in Table 14.
—
28–29
—
—
Reserved. Write to 0 fro future compatibility.
DFBRG
30–31
01
Unaffected
Division Factor for the BRG Clock Defines the
BRGCLK frequency. Changing this value does not
result in a loss of lock condition.
00
Divide by 4
01
Divide by 16 (default value)
10
Divide by 64
11
Divide by 256
Table 13. 2K42A Mask Set Clock Configuration Modes
Mode #
MODCK_H
MODCK[1–3]
SPLL
PDF
SPLL MF
Bus DF
Ratio
Bus:CPM:Core
Bus/
CLKIN
46
101
110
2
16
4
1 : 2 : 4
4
57
111
001
2
10
5
1 : 2.5 : 5
1
Table 14. 2K87M Mask Set Clock Configuration Modes
Mode #
MODCK_H1
MODCK[1–3]2
SPLL
PDF
SPLL
MF
Bus
DF
Core
DF
CPM
DF
CPLL
PDF
CPLL
MF
Ratio
Bus:CPM:Core
Bus/
CLKIN
0
000
000
1
12
4
4
2
4
12
1 : 2 : 3
3
1
000
001
2
16
4
4
2
4
12
1 : 2 : 3
2
2
000
010
Reserved
3
000
011
Reserved
4
000
100
2
16
4
4
2
4
14
1 : 2 : 3.5
2
5
000
101
1
12
4
2
2
5
10
1 : 2 : 4
3
6
000
110
3
12
4
2
2
5
10
1 : 2 : 4
1
7
000
111
1
10
5
5
2
2
10
1 : 2.5 : 5
2
8
001
000
1
16
4
4
2
4
12
1 : 2 : 3
4
9
001
001
1
20
4
4
2
4
12
1 : 2 : 3
5
10
001
010
3
12
4
4
2
4
12
1 : 2 : 3
1
11
001
011
3
12
4
4
2
4
14
1 : 2 : 3.5
1
12
001
100
1
12
4
4
2
4
14
1 : 2 : 3.5
3
13
001
101
1
16
4
4
2
4
14
1 : 2 : 3.5
4
14
001
110
Reserved
15
001
111
Reserved
16
010
000
1
12
6
2
2
5
10
1 : 3 : 6
2
17
010
001
2
12
6
2
2
5
10
1 : 3 : 6
1
18
010
010
1
16
8
8
2
2
12
1 : 4 : 6
2
19
010
011
2
16
8
8
2
2
12
1 : 4 : 6
1
20
010
100
Reserved
21
010
101
Reserved
Table 12. SCCR Bit Descriptions (Continued)
Name
Bit No.
Defaults
Description
Settings
PORESET
Hard Reset



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