EB632 datasheet(72/112 Pages) FREESCALE

72 / 112 page

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Errata

CPM100

ABR TCTE Address Miscalculation

Description: When using the AAL5 ABR ROM microcode with external ATM channels it is pos-

sible for the EXT_TCTE_BASE word value (written by the user to DPRAM) to be misread. In

this case calculations performed by the microcode to access the users programmed external TCTE

will be incorrect with a high chance of the access resulting in a CPM crash.

Workaround: Use the micro code patch available from Freescale.

System Number: 9131

Fix Plan: Rev. A

0K42A

1K42A

2K42A

CPM110

FCC1 Prioritization

Date Added: 12/19/2003

Description: The FCC1 receiver in Ethernet, HDLC, or Transparent controller mode is not ele-

vated to emergency status (priority 4 in Table 19-2 of the Reference Manual, "Peripheral Prioriti-

zation"), which may lead to a FIFO overrun if the system is heavily loaded (FCC1 receiver has the

highest priority excluding emergency status of other peripherals)

Workaround: When allocating FCCs, assign FCC2 and FCC3 for Ethernet, HDLC or Transpar-

ent before FCC1, or assign FCC1 to the lowest bit rate interface. If FCC1 is allocated for ATM

and requires higher CPM usage than the other FCCs, disable its emergency status.

System Number: 11062

Fix Plan:

0K40A

1K42A

2K42A

Table 49. Errata Resolved by Specification Change in Mask Set 2K87M

Errata

Number

Errata Description

Applies

to Mask

QSIU8

Core TEA Not Supported as NMI

Date Added: 9/7/2000

Description: Q2PPC TEA is not supported on PIC NMI5.

Workaround: Use PIC IRQ19.

Resolution: Specification is changed to reflect this state in mask set 2K87M.

0K40A

1K42A

2K42A

2K87M

SIU15

Data Not Written to the SDRAM in RMW Parity Mode

Date Added: 5/21/2002

Description: When using a read-modify-write parity mode and pipelined addresses on the

SDRAM interface, the write portion of the RMW might be performed as a read. As a result, the

data is not written to the external memory.

Workaround: Use BCR[PLDP]=1 for a pipeline depth of zero.

Fix Plan: None, specification is changed so that this is defined as normal functionality and be-

comes a documentation errata.

2K87M

Table 48. Errata Resolved in Mask Set 2K87M (Continued)

Errata

Number

Errata Description

Applies

to Mask

EB632 Datasheet(PDF) 72 Page - Freescale Semiconductor, Inc

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