EB632 datasheet(7/112 Pages) FREESCALE

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Reset

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

The major features of the reduce reset configuration include:

•

The MSC8103 samples the signals described in Table 6 at the rising edge of PORESET. If the configured boot

mode is serial, the values for the NMI_OUT, ISB, SWDIS, and DLLDIS fields are programmed from the

system data bus. The mapping of the bits on the data bus is the same as for hardware reset configuration mode.

•

MODCK_H cannot be programmed using this method and the value is set by default to 000. Therefore, only

clock modes 0–1 and 4–7 can be used with this boot mode.

•

In reduced configuration mode, the internal reset is extended for 1024 CLKIN cycles.

•

Although there is no default HRCW in this mode, the bits in the HRCW that are not programmed assume the

default values.

•

During the first 8 CLKIN cycles D[12–15] and D[26–27] are sampled to configure the NMI_OUT, ISB, SWDIS,

and DLLDIS fields in the HRCW. All other data bus bits are ignored. The simplest configuration scenario,

where all data bus pins are ignored is not available for this mode.

•

HRESET

in simple slave mode does not change the reset configuration. In master/slave mode, HRESET does

cause a new reset configuration.

•

Configuration from EPROM for single or multiple chip is available only for the mentioned above 6 bits. All

other bits on data bus are ignored.

•

Multiple chip configuration in a system with no EPROM is also available only for the mentioned above 6 bits.

All other bits on data bus are ignored.

4.2

Hard Reset Configuration Word Changes

The 2K87M mask set of the MSC8103 adds the SWDIS field (bit 26) and changes the definition of the ISB field

(bits 13–15).

MSC8103 2K87M Mask Set Hard Reset Configuration Word

Bit

EARB EXMC

IRQ7

INT

EBM

BPS

SCDIS

ISPS

IRPC

DPPC

NMI

OUT

ISB

Type

R/W

Reset

Bit

1617

192021

232425

272829

—

BBD

MMR

—

TCPC

BC1PC

SWDIS DLLDIS

MODCK_H

—

Type

R/W

Reset

Table 7. MSC8103 2K87M Mask Set Hard Reset Configuration Word Bit Descriptions

Name

Reset

Description

Settings

EARB

External Arbitration

Defines the initial value for PPC_ACR[EARB].

0 = No external arbitration is assumed

1 = External arbitration is assumed

EXMC

External MEMC

Defines the initial value of BR0[EMEMC].

0 = No external memory controller is assumed

1 = External memory controller is assumed

IRQ7 INT

IRQ7 or INT_OUT Selection

0 = IRQ7/INT_OUT pin is IRQ7

1 = IRQ7/INT_OUT pin is INT_OUT

EBM

External 60x-compatible Bus Mode

Defines the initial value of BCR[EBM].

BPS

4–5

Boot Port Size

Defines the initial value of BR0[PS], the port size for memory

controller bank 0.

00 = 64-bit port size

01 = 8-bit port size

10 = 16-bit port size

11 = 32-bit port size

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