AD9271 datasheet(37/58 Pages) AD

37 / 58 page

Preliminary Technical Data

AD9271

Rev. PrA | Page 37 of 58

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations.

The memory map is roughly divided into three sections: chip

configuration register map (Address 0x00 to Address 0x02), device

index and transfer register map (Address 0x05 and Address 0xFF),

and program register map (Address 0x08 to Address 0x25).

The left most column of the memory map indicates the register

address number, and the default value is shown in the right most

column. The (MSB) Bit 7 column is the start of the default hexa-

decimal value given. For example, Address 0x09, clock, has a

default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0,

Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in

binary. This setting is the default for the duty cycle stabilizer in

the on condition. By writing a 0 to Bit 6 of this address followed

by an 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer

turns off. It is important to follow each writing sequence with a

transfer bit to update the SPI registers. For more information on

this and other functions, consult the user manual Interfacing to

High Speed ADCs via SPI.

RESERVED LOCATIONS

Undefined memory locations should not be written to except

when writing the default values suggested in this data sheet.

Addresses that have values marked as 0 should be considered

reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

After a reset, critical registers are automatically loaded with

default values. These values are indicated in Table 16, where an

X refers to an undefined feature.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

AD9271 Datasheet(PDF) 37 Page - Analog Devices