AD9271 datasheet(32/58 Pages) AD

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AD9271

Preliminary Technical Data

Rev. PrA | Page 32 of 58

Two output clocks are provided to assist in capturing data from

the AD9271. The DCO is used to clock the output data and is

equal to six times the sampling clock (CLK) rate. Data is

clocked out of the AD9271 and must be captured on the rising

and falling edges of the DCO that supports double data rate

(DDR) capturing. The frame clock out (FCO) is used to signal

the start of a new output byte and is equal to the sampling clock

rate. See the timing diagram shown in Figure 2 for more

information.

Table 12. Flex Output Test Modes

Output Test

Mode Bit

Sequence

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject

to Data

Format

Select

0000

Off (default)

N/A

0001

Midscale short

1000 0000 (8 bits)

10 0000 0000 (10 bits)

1000 0000 0000 (12 bits)

10 0000 0000 0000 (14 bits)

Same

Yes

0010

+Full-scale short

1111 1111 (8 bits)

11 1111 1111 (10 bits)

1111 1111 1111 (12 bits)

11 1111 1111 1111 (14 bits)

Same

Yes

0011

−Full-scale short

0000 0000 (8 bits)

00 0000 0000 (10 bits)

0000 0000 0000 (12 bits)

00 0000 0000 0000 (14 bits)

Same

Yes

0100

Checkerboard

1010 1010 (8 bits)

10 1010 1010 (10 bits)

1010 1010 1010 (12 bits)

10 1010 1010 1010 (14 bits)

0101 0101 (8 bits)

01 0101 0101 (10 bits)

0101 0101 0101 (12 bits)

01 0101 0101 0101 (14 bits)

0101

PN sequence long1

N/A

Yes

0110

PN sequence short1

N/A

Yes

0111

One/zero word toggle

1111 1111 (8 bits)

11 1111 1111 (10 bits)

1111 1111 1111 (12 bits)

11 1111 1111 1111 (14 bits)

0000 0000 (8 bits)

00 0000 0000 (10 bits)

0000 0000 0000 (12 bits)

00 0000 0000 0000 (14 bits)

1000

User input

1001

One/zero bit toggle

1010 1010 (8 bits)

10 1010 1010 (10 bits)

1010 1010 1010 (12 bits)

10 1010 1010 1010 (14 bits)

N/A

1010

1× sync

0000 1111 (8 bits)

00 0001 1111 (10 bits)

0000 0011 1111 (12 bits)

00 0000 0111 1111 (14 bits)

N/A

1011

One bit high

1000 0000 (8 bits)

10 0000 0000 (10 bits)

1000 0000 0000 (12 bits)

10 0000 0000 0000 (14 bits)

N/A

1100

Mixed frequency

1010 0011 (8 bits)

10 0110 0011 (10 bits)

1010 0011 0011 (12 bits)

10 1000 0110 0111 (14 bits)

N/A

1 All test mode options, except PN Sequence Short and PN Sequence Long, can support 8- to 14-bit word lengths in order to verify data capture to the receiver.

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