AD9271 datasheet(33/58 Pages) AD

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Preliminary Technical Data

AD9271

Rev. PrA | Page 33 of 58

When using the serial port interface (SPI), the DCO phase can

be adjusted in 60° increments relative to the data edge. This

enables the user to refine system timing margins if required.

The default DCO timing, as shown in Figure 2, is 90° relative to

the output data edge.

An 8-, 10-, and 14-bit serial stream can also be initiated from

the SPI. This allows the user to implement different serial streams

and test the device’s compatibility with lower and higher resolution

systems. When changing the resolution to an 8- or 10-bit serial

stream, the data stream is shortened. When using the 14-bit

option, the data stream stuffs two 0s at the end of the normal

14-bit serial data.

When using the SPI, all of the data outputs can also be inverted

from their nominal state. This is not to be confused with

inverting the serial stream to an LSB-first mode. In default

mode, as shown in Figure 2, the MSB is represented first in the

data output serial stream. However, this can be inverted so that

the LSB is represented first in the data output serial stream (see

Figure 3).

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. Refer to Table 12 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen. It should be noted

that some patterns may not adhere to the data format select

option. In addition, customer user patterns can be assigned in

the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode

options, except PN Sequence Short and PN Sequence Long can

support 8- to 14-bit word lengths in order to verify data capture

to the receiver.

The PN Sequence Short pattern produces a pseudorandom bit

sequence that repeats itself every 29 – 1 or 511 bits. A

description of the PN sequence and how it is generated can be

found in section 5.1 of the ITU-T 0.150 (05/96) standard. For

the AD9271, the only discrepancy from the ITU standard is that

the starting value is a specific value instead of all ones. See

Table 10 for initial values.

The PN Sequence Long pattern produces a pseudorandom bit

sequence that repeats itself every 223 – 1 or 8,388,607 bits. A

description of the PN sequence and how it is generated can be

found in section 5.6 of the ITU-T 0.150 (05/96) standard. The

only two discrepancies between the ITU standard and the

AD9271 PN Sequence Long implementation are as follows.

First, the starting value is a specific value instead of all ones.

Second, the AD9271 inverts the bit stream with relation to the

ITU standard. See Table 10 for initial values.

Table 10. PN Sequence

Initial Value

First 3 output samples

(MSB 1st)

PN Sequence

Short

0x0df

0xdf9, 0x353, 0x301

PN Sequence

Long

0x29b80a

0x591, 0xfd7, 0a3

Consult the Memory Map section for information on how to

change these additional digital output timing features through the

serial port interface or SPI.

SDIO Pin

This pin is required to operate the SPI port interface. It has an

internal 30 kΩ pull-down resistor that pulls this pin low and is

only 1.8 V tolerant. If applications require that this pin be driven

from a 3.3 V logic level, insert a 1 kΩ resistor in series with this

pin to limit the current.

SCLK Pin

This pin is required to operate the SPI port interface. It has an

internal 30 kΩ pull-down resistor that pulls this pin low and is

both 1.8 V and 3.3 V tolerant.

CSB Pin

This pin is required to operate the SPI port interface. It has an

internal 70 kΩ pull-down resistor that pulls this pin low and is

both 1.8 V and 3.3 V tolerant.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor

(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The

resistor current is derived on-chip and sets the ADC’s AVDD

current to a nominal xxx mA at 50 MSPS. Therefore, it is

imperative that at least a 1% tolerance on this resistor be used to

achieve consistent performance.

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the

AD9271. This is gained up internally by a factor of 2, setting

VREF to 1.0 V, which results in a full-scale differential input span

of 2 V p-p for the ADC. The VREF is set internally by default;

however, the VREF pin can be driven externally with a 1.0 V

reference to achieve more accuracy.

When applying the decoupling capacitors to the VREF, REFT,

and REFB pins, use ceramic low ESR capacitors. These capacitors

should be close to reference pins and on the same layer of the

PCB as the AD9271. The recommended capacitor values and

configurations for the AD9271 reference pin can be found in

Figure 58.

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