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AD9271

Preliminary Technical Data

Rev. PrA | Page 30 of 58

Power Dissipation and Power-Down Mode

As shown in Figure 52, the power dissipated by the AD9271 is

proportional to its sample rate. The digital power dissipation

does not vary much because it is determined primarily by the

DRVDD supply and bias current of the LVDS output drivers.

100

200

300

400

500

600

700

800

1020

30405060

Sampling Frequency (MSPS)

25MSPS Speed Grade

40MSPS Speed Grade

50MSPS Speed Grade

IDRVDD

Figure 52. Supply Current vs. fSAMPLE for fIN = 7.5 MHz

100

110

120

130

140

150

160

170

180

190

10203040

5060

Sampling Frequency (MSPS)

25MSPS Speed Grade

40MSPS Speed Grade

50MSPS Speed Grade

Figure 53. Power per Channel vs. fSAMPLE for fIN = 7.5 MHz

By asserting the PDWN pin high, the AD9271 is placed in

power-down mode. In this state, the ADC typically dissipates

xx mW. During power-down, the LVDS output drivers are placed

in a high impedance state. The AD9271 returns to normal

operating mode when the PDWN pin is pulled low. This pin is

both 1.8 V and 3.3 V tolerant.

By asserting the STBY pin high, the AD9271 is placed in a

standby mode. In this state, the ADC typically dissipates

xx mW. During standby, the entire part is powered down except

the internal references. The LVDS output drivers are placed in a

high impedance state. This mode is well suited for applications

that require power savings because it allows the device to be

powered down when not in use and then quickly powered up.

The time to power this device back up is also greatly reduced. The

AD9271 returns to normal operating mode when the STBY pin

is pulled low. This pin is both 1.8 V and 3.3 V tolerant.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode; shorter cycles result in proportionally shorter wake-up

times. With the recommended 0.1 μF and 4.7 μF decoupling

capacitors on REFT and REFB, it takes approximately 1 sec to

fully discharge the reference buffer decoupling capacitors and

xx μs to restore full operation.

There are a number of other power-down options available

when using the SPI port interface. The user can individually

power down each channel or put the entire device into standby

mode. This allows the user to keep the internal PLL powered up

when fast wake-up times (~xxx ns) are required. See the

Memory Map section for more details on using these features.

Digital Outputs and Timing

The AD9271 differential outputs conform to the ANSI-644 LVDS

standard on default power-up. This can be changed to a low power,

reduced signal option similar to the IEEE 1596.3 standard using the

SDIO/ODM pin or via the SPI. This LVDS standard can further

reduce the overall power dissipation of the device by approximately

xx mW. See the SDIO Pin section or Table 16 in the Memory

Map section for more information. The LVDS driver current is

derived on-chip and sets the output current at each output equal

to a nominal 3.5 mA. A 100 Ω differential termination resistor

placed at the LVDS receiver inputs results in a nominal 350 mV

swing at the receiver.

The AD9271 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments.

Single point-to-point net topologies are recommended with a

100 Ω termination resistor placed as close to the receiver as

possible. No far-end receiver termination and poor differential

trace routing may result in timing errors. It is recommended

that the trace length is no longer than 24 inches and that the

differential output traces are kept close together and at equal

lengths. An example of the FCO and data stream with proper

trace length and position can be found in Figure 54.

AD9271 Datasheet(PDF) 30 Page - Analog Devices

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