AD9271 datasheet(27/58 Pages) AD

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Preliminary Technical Data

AD9271

Rev. PrA | Page 27 of 58

noise of the LNA and source prevail. The input-referred noise

reaches its minimum value near the maximum gain control

voltage, where the input-referred contribution of the VGA is

miniscule.

At lower gains, the input-referred noise, and therefore the noise

figure, increases as the gain decreases. The instantaneous

dynamic range of the system is not lost, however, because the

input capacity increases as the input-referred noise increases.

The contribution of the ADC noise floor has the same

dependence. The important relationship is the magnitude of the

VGA output noise floor relative to that of the ADC.

Gain control noise is a concern in very low noise applications.

Thermal noise in the gain control interface can modulate the

channel gain. The resultant noise is proportional to the output

signal level and usually only evident when a large signal is present.

The gain interface includes an on-chip noise filter, which reduces

this effect significantly at frequencies above 5 MHz. Care should be

taken to minimize noise impinging at the GAIN input. An external

RC filter can be used to remove VGAIN source noise. The filter band-

width should be sufficient to accommodate the desired control

bandwidth.

Antialiasing Filter

The filter that the signal reaches prior to the ADC is used to

reject dc signals and to bandlimit the signal for antialiasing.

Figure 45 shows the architecture of the filter.

2kΩ

*C = 0.5 TO 3.1pF

6.5C*

7.5C*

1C*

4kΩ

56/112pF

Figure 45. Simplified Filter Schematic

The filter can be configured for dc coupling or to have a single

pole for high-pass filtering at either 700 kHz or 350 kHz

(programmed through the SPI). The high-pass pole, however, is

not tuned and can vary by ±30%.

A third-order Butterworth low-pass filter is used to reduce

noise bandwidth and provide antialiasing for the ADC. The

filter uses on-chip tuning to trim the capacitors to set the

desired cutoff and reduce variation. The default −3dB cutoff is

1/3 the ADC sample clock rate. The cutoff can be scaled to 0.7,

0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI.

The cutoff can be set from 8 MHz to 18 MHz.

Tuning is normally off to avoid changing the capacitor settings

during critical times. The tuning circuit is enabled and disabled

through the SPI. Tuning should be done after initial power-up

and after reprogramming the filter cutoff scaling or ADC

sample rate. Occasional retuning during an idle time is

recommended.

AD9271 Datasheet(PDF) 27 Page - Analog Devices

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