AD9271 datasheet(38/58 Pages) AD

38 / 58 page

AD9271

Preliminary Technical Data

Rev. PrA | Page 38 of 58

Table 16. Memory Map Register

Addr.

(Hex)

Parameter Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default Notes/

Comments

Chip Configuration Registers

chip_port_config

LSB first

1 = on

0 = off

(default)

Soft

reset

1 = on

0 = off

(default)

Soft

reset

1 = on

0 = off

(default)

LSB first

1 = on

0 = off

(default)

0x18

The nibbles

should be

mirrored so that

LSB- or MSB-first

mode registers

correctly

regardless of

shift mode.

chip_id

Chip ID Bits 7:0

(AD9271 = 0x13), (default)

Read

only

Default is unique

chip ID, different

for each device.

This is a read-only

chip_grade

Child ID 6:4

(identify device

variants of Chip ID)

00 = 50 MSPS

(default)

01 = 40 MSPS

11 = 25 MSPS

0x00

Child ID used to

differentiate

graded devices.

Device Index and Transfer Registers

device_index_2

Data

Channel

1 = on

(default)

0 = off

Data

Channel

1 = on

(default)

0 = off

Data

Channel

1 = on

(default)

0 = off

Data

Channel

1 = on

(default)

0 = off

0x0F

Bits are set to

determine which

on-chip device

receives the next

write command.

device_index_1

Clock

Channel

DCO

1 = on

0 = off

(default)

Clock

Channel

FCO

1 = on

0 = off

(default)

Data

Channel

1 = on

(default)

0 = off

Data

Channel

1 = on

(default)

0 = off

Data

Channel

1 = on

(default)

0 = off

Data

Channel

1 = on

(default)

0 = off

0x0F

Bits are set to

determine which

on-chip device

receives the next

write command.

device_update

transfer

1 = on

0 = off

(default)

0x00

Synchronously

transfers data

from the master

shift register to

the slave.

ADC Functions

modes

LNA

bypass

1 = on

0 = off

(default)

Internal power-down mode

000 = chip run (default)

001 = full power-down

010 = standby

011 = reset

100 = CW mode (TGC PWDN)

0x00

Determines

various generic

modes of chip

operation.

clock

Duty

cycle

stabilizer

1 = on

(default)

0 = off

0x01

Turns the internal

duty cycle stabilizer

on and off.

test_io

User test mode

00 = off (default)

01 = on, single

alternate

10 = on, single once

11 = on, alternate once

Reset PN

long

gen

1 = on

0 = off

(default)

Reset

short

gen

1 = on

0 = off

(default)

Output test mode—see Table 12 in the

Digital Outputs and Timing section

0000 = off (default)

0001 = midscale short

0010 = +FS short

0011 = −FS short

0100 = checkerboard output

0101 = PN 23 sequence

0110 = PN 9

0111 = one/zero word toggle

1000 = user input

1001 = one/zero bit toggle

0x00

When set, the test

data is placed on

the output pins in

place of normal

data. (Local,

expect for PN

sequence)

AD9271 Datasheet(PDF) 38 Page - Analog Devices

AD9271 Datasheet(HTML) 38 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL