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AD9271

Preliminary Technical Data

Rev. PrA | Page 28 of 58

A/D CONVERTER

The AD9271 architecture consists of a pipelined ADC that is

divided into three sections: a 4-bit first stage followed by eight

1.5-bit stages and a 3-bit flash. Each stage provides sufficient

overlap to correct for flash errors in the preceding stages. The

quantized outputs from each stage are combined into a 12-bit

result in the digital correction logic. The pipelined architecture

permits the first stage to operate on a new input sample and the

remaining stages to operate on preceding samples. Sampling

occurs on the rising edge of the clock.

Each stage except for the last of the pipeline consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage consists of a flash ADC.

The output staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The data is

then serialized and aligned to the frame and output clock.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9271 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional bias.

Figure 46 shows the preferred method for clocking the AD9271.

The low jitter clock source, such as the Valpey Fisher oscillator

VFAC3-BHL-50MHz, is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9271 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9271 and preserves the fast

rise and fall times of the signal, which are critical to low jitter

performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω 100Ω

CLK–

CLK+

ADC

AD9271

MINI-CIRCUITS

ADT1–1WT, 1:1Z

XFMR

VFAC3

OUT

Figure 46. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a

differential PECL signal to the sample clock input pins as shown

in Figure 47. The AD951x family of clock drivers offers excellent

jitter performance.

100Ω

0.1µF

240Ω

AD951x FAMILY

50Ω*

CLK

*50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9271

PECL DRIVER

3.3V

OUT

VFAC3

Figure 47. Differential PECL Sample Clock

100Ω

0.1µF

50Ω*

LVDS DRIVER

CLK

*50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9271

AD951x FAMILY

3.3V

OUT

VFAC3

Figure 48. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be driven directly from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 48). Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages up to 3.3 V, making the

selection of the drive logic voltage very flexible.

0.1µF

39kΩ

CMOS DRIVER

50Ω*

OPTIONAL

100Ω

0.1µF

CLK

*50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9271

AD951x FAMILY

3.3V

OUT

VFAC3

Figure 49. Single-Ended 1.8 V CMOS Sample Clock

0.1µF

CMOS DRIVER

50Ω*

OPTIONAL

100Ω

CLK

*50Ω RESISTOR IS OPTIONAL.

0.1µF

CLK–

CLK+

ADC

AD9271

AD951x FAMILY

3.3V

OUT

VFAC3

Figure 50. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance

is required on the clock duty cycle to maintain dynamic

performance characteristics. The AD9271 contains a duty cycle

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