AD9271 datasheet(29/58 Pages) AD

29 / 58 page

Preliminary Technical Data

AD9271

Rev. PrA | Page 29 of 58

stabilizer (DCS) that retimes the nonsampling edge, providing

an internal clock signal with a nominal 50% duty cycle. This

allows a wide range of clock input duty cycles without affecting

the performance of the AD9271. When the DCS is on, noise

and distortion performance are nearly flat for a wide range of

duty cycles. However, some applications may require the DCS

function to be off. If so, keep in mind that the dynamic range

performance can be affected when operated in this mode. See the

Memory Map section for more details on using this feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately eight clock cycles

to allow the DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter. IF undersampling applications

are particularly sensitive to jitter (see Figure 51).

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9271.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources, such as the Valpey Fisher VFAC3 series.

If the clock is generated from another type of source (by gating,

dividing, or other methods), it should be retimed by the

original clock at the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs (visit www.analog.com).

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

0.25ps

Figure 51. Ideal SNR vs. Input Frequency and Jitter

AD9271 Datasheet(PDF) 29 Page - Analog Devices

AD9271 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL