AD9271 datasheet(43/58 Pages) AD

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Preliminary Technical Data

AD9271

Rev. PrA | Page 43 of 58

DEFAULT OPERATION AND JUMPER SELECTION

SETTINGS

The following is a list of the default and optional settings or

modes allowed on the AD9271 Rev. A evaluation board.

•

POWER: Connect the switching power supply that is

supplied in the evaluation kit between a rated 100 V ac

to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.

•

AIN: The evaluation board is set up for a transformer-

coupled analog input with optimum 50 Ω impedance

matching out to 18 MHz (see Figure 66). For a different

bandwidth response, change the 22 pF capacitor at the

LNA (LI-x) analog input.

Figure 66. Evaluation Board Full Power Bandwidth

•

VREF: VREF is set to 1.0 V by tying the SENSE pin to

ground, R317. This causes the ADC to operate in 2.0 V p-p

full-scale range. A separate external reference option using

the ADR510 or ADR520 is also included on the evaluation

board. Populate R311 and R315 with 0 Ω resistors and

remove C307. Proper use of the VREF options is noted in

the Voltage Reference section.

•

RBIAS: RBIAS has a default setting of 10 kΩ (R301) to

ground and is used to set the ADC core bias current. To

further lower the core power (excluding the LVDS driver

supply), change the resistor setting. However, performance

of the ADC may degrade depending on the resistor chosen.

See RBIAS section for more information.

•

CLOCK: The default clock input circuitry is derived from a

simple transformer-coupled circuit using a high bandwidth

1:1 impedance ratio transformer (T401) that adds a very

low amount of jitter to the clock path. The clock input is

50 Ω terminated and ac-coupled to handle single-ended

sine wave types of inputs. The transformer converts the

single-ended input to a differential signal that is clipped

before entering the ADC clock inputs.

The evaluation board is already set up to be clocked from the

crystal oscillator, OSC401. This oscillator is a low phase noise

oscillator from Valpey Fisher (VFAC3-BHL-50MHz). If a

different clock source is desired, remove R403, set Jumper

J401 to disable the oscillator from running, and connect the

external clock source to the SMA connector, P401.

A differential LVPECL clock driver can also be used to

clock the ADC input using the AD9515 (U401). Populate

R406 and R407 with 0 Ω resistors and remove R415 and

R416 to disconnect the default clock path inputs. In addition,

populate C405 and C406 with a 0.1 μF capacitor and remove

C409 and C410 to disconnect the default cloth path outputs.

The AD9515 has many pin-strappable options that are set

to a default mode of operation. Consult the AD9515 data

sheet for more information about these and other options.

•

PDWN: To enable the power-down feature, short P303 to

the on position (AVDD) on the PDWN pin.

•

STDBY: To enable the standby feature, simply short P302

to the on position (AVDD) on the STDBY pin.

•

GAIN: To change the gain on the VGA, drive these pins

from 0 V to 1 V on J301. This changes the VGA gain from

0 dB to 30 dB. This feature can also be driven from the

R335 and R336 on-board resistive dividers by installing a

0 Ω resistor in R337.

•

Non-SPI Mode: For users who wish to operate the DUT

without using SPI, remove the jumpers on J501. This

disconnects the CSB, SCLK, and SDIO pins from the control

bus, allowing the DUT to operate in its simplest mode. Each

of these pins has internal termination and will float to its

respective level. Note that the device will only work in its

default condition.

•

CWD+,CWD−: To view muiltple CW outputs, jumper

together the appropriate outputs on P403 and P404. All

outputs are summed together on IOP and ION buses, fed

to a 1:4 impedance ratio transformer, and buffered so that

the user can view the output on a spectrum analyzer. This

can be configured to be viewed in single-ended mode

(default) or in differential mode. To set the voltage for the

appropriate number of channels to be summed, change the

value of R447 and R448 on the primary transformer

(T402).

•

D+, D−: If an alternative data capture method to the setup

described in Figure 67 is used, optional receiver terminations,

R318, R320 to R330, can be installed next to the high speed

backplane connector.

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