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Preliminary Technical Data

AD9271

Rev. PrA | Page 31 of 58

Figure 54. LVDS Output Timing Example in ANSI Mode (Default)

An example of the LVDS output using the ANSI standard (default)

data eye and a time interval error (TIE) jitter histogram with

trace lengths of less than 24 inches on regular FR-4 material is

shown in Figure 55. Figure 56 shows an example of when the

trace lengths exceed 24 inches on regular FR-4 material. Notice

that the TIE jitter histogram reflects the decrease of the data eye

opening as the edge deviates from the ideal position; therefore,

the user must determine if the waveforms meet the timing budget

of the design when the trace lengths exceed 24 inches. Additional

SPI options allow the user to further increase the internal

termination (and therefore increase the current) of all eight

outputs in order to drive longer trace lengths (see Figure 57).

Even though this produces sharper rise and fall times on the

data edges, is less prone to bit errors, and improves frequency

distribution (see Figure 57), the power dissipation of the DRVDD

supply increases when this option is used.

In cases that require increased driver strength to the DCO and

FCO outputs because of load mismatch Register 15 allows the

user to double the drive strength. To do this, set the appropriate

bit in Register 5. Note that this feature cannot be used with Bit 4

and Bit 5 in Register 15 because these bits take precedence over

this feature. See the Memory Map section for more details.

Figure 55. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths of

Less than 24 Inches on Standard FR-4

Figure 56. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths of

Greater than 24 Inches on Standard FR-4

Figure 57. Data Eye for LVDS Outputs in ANSI Mode with 100 Ω Termination

on and Trace Lengths of Greater than 24 Inches on Standard FR-4

The format of the output data is offset binary by default. An

example of the output coding format can be found in Table 11.

If it is desired to change the output data format to twos

complement, see the Memory Map section.

Table 11. Digital Output Coding

Code

(VIN+) − (VIN−), Input

Span = 2 V p-p (V)

Digital Output Offset Binary

(D11 ... D0)

4095

+1.00

1111 1111 1111

2048

0.00

1000 0000 0000

2047

−0.000488

0111 1111 1111

−1.00

0000 0000 0000

Data from each ADC is serialized and provided on a separate

channel. The data rate for each serial stream is equal to 12 bits

times the sample clock rate, with a maximum of 600 Mbps

(12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion

rate is 10 MSPS. However, if lower sample rates are required for

a specific application, the PLL can be set up for encode rates

lower than 10 MSPS via the SPI. This allows encode rates as low

as 5 MSPS. See the Memory Map section for details on enabling

this feature.

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