ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

22 of 55

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I2C INTERFACE ELECTRICAL CHARACTERISTICS

(AVIN = 3.3V, Tj = -40°C to +125°C, unless otherwise specified.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SCL, SDA Input Low

AVIN = 3.3V

0.4

V

SCL, SDA Input High

AVIN = 3.3V

1.25

V

SDA Leakage Current

SDA=5V

1

µA

SDA Output Low

IOL = 5mA

0.35

V

SCL Clock Frequency, fSCL

0

1000

kHz

SCL Low Period, tLOW

0.5

µs

SCL High Period, tHIGH

0.26

µs

SDA Data Setup Time, tSU

50

ns

SDA Data Hold Time, tHD

(Note1)

0

ns

Start Setup Time, tST

For Start Condition

260

ns

Stop Setup Time, tSP

For Stop Condition

260

ns

Capacitance on SCL or SDA Pin

10

pF

SDA Fall Time SDA, Tof

Device requirement

120

ns

Pulse Width of spikes must be suppressed on SCL and SDA

0

50

ns

Note1: Comply to I2C timings for 1MHz operation - “Fast Mode Plus”.

Note2: No internal timeout for I2C operations, however, I2C communication state machine will be reset when entering RESET, IDLE, OVUVFLT, and

THERMAL states to clear any transactions that may have been occurring when entering the above states.

Note3: This is an I2C system specification only. Rise and fall time of SCL & SDA not controlled by the device.

Note4: Device Address is 7’h5A

Figure 2: I2C Data Transfer

SDA

SCL

tST

tSU

tHD

tSP

tSCL

Start

condition

Stop

condition