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ACT88321 Datasheet(PDF) 33 Page - Qorvo, Inc |
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ACT88321 Datasheet(HTML) 33 Page - Qorvo, Inc |
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33 / 55 page ![]() ACT88321 Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches Datasheet Rev. D , June 17, 2022 | Subject to change without notice 33 of 55 www.qorvo.com ® each pin. Examples of system functions that can be im- plemented are nRESET, Power Good (PG) output, in- terrupt request or interrupt pin (nIRQ), digital output from power okay (POK) signal from individual regulators, digital outputs to control external regulators (EXT_EN), digital input lines to monitor power good signals from external regulators (EXT_PG), digital input to control power sequencing or regulator ON/Off, control input used to enter or exit sleep (SLEEP) and deep sleep (DPSLP) modes, inputs to control Dynamic Voltage Scaling (DVS) in the Buck regulators, Buck1 bypass mode selection, and outputs for the SYSMON and SYMWARN functions. All GPIOs are capable of the functionality described above. All GPIOs are 5V compli- ant and can be pulled to 5V regardless of their bias sup- ply. SCL, SDA These are the I2C clock and data pins to the IC. They have standard I2C functionality. The SCL and SDA pins have dedicated functionality and cannot be used for other functionality. If I2C is not needed, these pins should be tied to either ground or to AVIN. PGNDx The PGNDx pins are the buck converter power ground pins. They connect directly to the buck converters’ low side FETs. SW_Bx SWx are the switch nodes for the buck converters. They connect directly to the buck inductor on the top layer. FB_Bx These are the feedback pins for the buck regulators. They should be kelvin connected to the buck output ca- pacitors. LDOx These are the LDO output pins. Each LDO output must be bypassed to AGND with a 1uF capacitor. AGND AGND is the ground pin for the IC’s analog circuitry and LDOs. AGND must be connected to the IC’s PGNDx pins. The connection between AGND and the PGNDx pins should not have high currents flowing through it. |
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