ACT88321 datasheet(31/55 Pages) QORVO

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ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

31 of 55

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configured as an input to the nRESET output. This pre-

vents a regulator’s POK signal from triggering nRESET

when the regulator is commanded by the user to turn off

The ACT88321 RSTI_BY_POK (register 0xAE, bit 7) bit

defines this functionality. For outputs that are configured

to control the nRESET functionality (RST=1), if

RSTI_BY_POK=0 and the output is turned off, that out-

put does not assert nRESET low. If RSTI_BY_POK=1

and the output is turned off, it does assert nRESET low.

A regulator’s POK signal is typically low only from the

time when it is enabled (enable to the regulator goes

high) to the time when the output reaches 90% or higher

of the final output voltage. nRESET can be reconfigured

to any GPIO pin.

EXT_EN

The EXT_EN is a GPIO output function that is used to

enable an external power supply. This function is useful

for incorporating external power supplies into the overall

system level startup sequencing. The EXT_EN output

can be triggered by one of the regulator’s POK signals.

It can be programmed with a 0, 1, 5, or 10ms delay time

using the GPIOx’s I2C bits IOx_DLY in registers 0x0Bh

and 0x0Ch.

EXT_PG

The EXT_PG is a GPIO input function that is used to

determine that an external power supply has turned on

and its output voltage is in regulation. This function is

useful for incorporating external power supplies into the

overall system level startup sequencing. The EXT_PG

output can be used as an input trigger to turn on one of

the ACT88321 regulators.

POK

Any regulator’s internal POK bit can be connected to a

GPIO to provide an external POK signal. The POK func-

tion indicates that a regulator’s output voltage is in reg-

ulation.

ROM Mode

In SSD applications, there is a chance the firmware,

which is stored in the flash, is not loaded properly. In

this situation, the SSD fails to startup and work properly.

The SSD core must be put back into ROM mode to at-

tempt a restart. In some systems, this requires recycling

power, removing and reinserting the SSD card, or man-

ually shorting pins on the SSD module.

ACT88321 includes a ROM Mode feature that signifi-

cantly simplifies this process at a system level. The

ACT88321 ROM Mode forces the SSD core to stay in

its ROM state if it does not power up properly.

Figure 6 shows how ROM Mode is implemented. One

GPIO is configured as the input for the ISP Ready signal,

which is an output from the SSD core after the system

powers up. Another GPIO is configured as output for the

ROM state signal. After the ACT88321 startup se-

quence completes, the ACT88321 deasserts its nRE-

SET output and an internal watchdog timer starts mon-

itoring the ISP Ready input signal (active high) to make

sure system powers up successfully. If the ISP Ready

input is not asserted within 7s (configurable to 7s or 20s),

the ACT88321 starts the ROM mode. It turns off all reg-

ulator outputs, asserts nRESET low, and asserts the

ROM_Only signal low. After a 100ms (configurable be-

tween 100ms and 250ms) delay, the ACT88321 restarts

the power up sequence. The ROM_Only output stays

asserted low until nRESET is de-asserted high to make

sure the SSD core stays in the ROM state when pow-

ered up.

ROM mode is only activated after nRESET is deas-

serted. I2C bit NVM ROM_EN enables ROM mode. If

the SSD driver needs to enter a power save mode be-

fore the 7s watchdog timer expires, the host needs to

disable ROM mode before entering the power save

mode to avoid the potential risk of activating the

ROM_Only and nRESET outputs.

Watchdog Timer

The ACT88321 contains a watchdog timer to detect sys-

tem level communication failures. The watchdog timer

requires the host to periodically perform an I2C read or

write before the 7.4s watchdog timer expires. If I2C bit

WD_ALERT_MSK = 0 when the timer expired, nIRQ is

immediately pulled low and stays low until the

WD_ALERT bit is read.

If the I2C bit WDSREN = 1 when the timer expires, the

IC waits 800ms and then pulls the nRESET pin low for

20ms. Note that this does not affect the status of any

output voltages.

If the I2C bit WDPCEN = 1 when the timer expires, the

IC waits 800ms and then turns all outputs off for 500ms

before restarting the system. Note that all registers are

reset to their default startup values.

If the host performs an I2C read or write after the 7.4s

timeout but before nRESET is pulled low or the outputs

are turned off, the watchdog timer is reset.

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