ACT88321 datasheet(40/55 Pages) QORVO

40 / 55 page

ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

40 of 55

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retains overcurrent protection. Overvoltage and un-

dervoltage protection are disabled.

In load switch mode, LDO1 has two operating options:

NLSW and PLSW modes. In NLSW mode, the load

switch is an n-ch FET. NLSW mode is used with an in-

put voltage between 0.4V and AVIN-1V. Due to the

lower n-ch FET Rdson, NLSW mode can operate with

up to 1A of bypass current while maintaining a low volt-

age drop. The NLSW current limit is set to 0.65A or

1.11A by the NLSW1_ILIM_SCL I2C bit.

In PLSW mode, the load switch is a p-ch FET. It can

operate with an input voltage between 1.62V and AVIN.

The PLSW current limit is set to 0.33A or 0.48A by the

ILIM_SCL_LDO1 I2C bit.

NLSW and PLSW modes can only be fixed at the fac-

tory.

NLSW mode has a fixed 200µs softstart time. PLSW

mode relies on the current limit setting for softstart.

The LDO1 POK is functional in Load Switch mode. The

POK signal is asserted when the switch is enabled and

is not in current limit. In bypass mode, the over voltage

protection is set at 3.8V with a 10us deglitch time. If

VIN_LDO goes above 3.8V, the load switch is turned off

and retries after 100ms.

Unused LDO Outputs

If LDO1 is not used, connect the VIN_LDO pin to either

GND or AVIN. Connect the LDO1 output to AGND. The

input and output capacitors are not needed.

If LDO2 is not used, connect the LDO1 output to AGND.

The output capacitor is not needed, but the AVIN input

capacitor is still needed.

ACT88321 Datasheet(PDF) 40 Page - Qorvo, Inc