ACT88321 datasheet(29/55 Pages) QORVO

29 / 55 page

ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

29 of 55

www.qorvo.com

Input Voltage Warning (SYSWARN)

The ACT88321 also has a second level of input voltage

monitoring, SYSWARN. SYSWARN provides another

level of low input voltage warning to the host. Its rising

threshold is programmable between 2.7V and 5.7V with

100mV steps by the SYSWARN bits. A GPIO can be

programmed to output an active low SYSWARN signal

so the host can use it for system control purposes. In

the meantime, the IC asserts the nIRQ interrupt when

VIN < SYSWARN. The nIRQ interrupt can be masked

in the NVM register bit. The SYSWARN signal output is

a real-time signal. The IC also has a real-time status bit,

SYSWARN, that follows the internal SYSWARN signal.

Note that the nIRQ output is latched until the SYS-

WARN bit in register 0x00h is read via I2C.

Fault Protection

The ACT88321 contains several levels of fault protec-

tion, including the following:

Output Overvoltage

Output Undervoltage

Output Current Limit and Short Circuit

Thermal Warning

Thermal Shutdown

There are three types of I2C register bits associated with

each fault condition: fault flag bits, fault bits, and mask

bits. The fault flag bits display the real-time fault status.

Their status is valid regardless of whether that fault is

masked. The mask bits either block or allow the fault to

affect the fault bit. Each potential fault condition can be

masked via I2C if desired. Any unmasked fault condition

results in the fault bit going high, which asserts the nIRQ

pin. nIRQ is typically active low. The nIRQ pin only de-

asserts after the fault condition is no longer present and

the corresponding fault bit is read via I2C. Note that

masked faults can still be read in the fault flag bit. Refer

to the Qorvo Application Note describing the Register

Map for full details on I2C functionality and programming

ranges.

Input Voltage UVLO

The ACT88321 monitors its input voltage at the AVIN pin

for a UVLO condition. When the input voltage is below

the UVLO threshold, the IC is in the RESET State, all

outputs are turned off, and nRESET is asserted low. I2C

functionality is not enabled until AVIN goes above the

UVLO threshold. When the input voltage goes above

UVLO, the IC transitions to the ACTIVE state and starts

up normally. The UVLO threshold can be set to either

2.6V or 3.5V by a factory programmable bit, VIN_LVL.

VIN_LVL is not user adjustable.

Input Voltage OV

The ACT88321 monitors its input voltage at the AVIN pin

for an OV condition. There are two overvoltage levels,

POK_OV and VIN_OV. The first level is set by the

POK_OV register, which is programmable between

3.5V and 5.6V in 300mV steps. When AVIN goes above

the POK_OV threshold, an interrupt is generated on the

nIRQ

output,

but

all

outputs

stay

on.

VIN_POK_OV_MASK = 0, the VIN_POK_OV register

provides real-time status if. If it = 1, then VIN_POK_OV

VIN_OV, is programmable between 3.7V and 5.81V.

When the input voltage is above the VIN_OV threshold,

the IC is in the RESET State, all outputs are turned off,

and nRESET is asserted low. I2C functionality is still

enabled while AVIN is above the VIN_OV threshold.

When the input voltage goes below the VIN_OV

threshold, the IC transitions back to the Power

Sequence Start State and starts up normally.

Output Under/Over Voltage

When an output’s OV_FLTMSK and UV_FLTMSK (vol-

atile bits) = 0 and DISOVUVSD (0x09h[0])=0, the

ACT88321 monitors the output voltages for under volt-

age and over voltage conditions. If one output enters an

UV/OV fault condition, the IC enters the OVUV Fault

State and shuts down all outputs for 100ms. It then en-

ters the POWER START SEQUENCE State and re-

starts with the programmed power up sequence. If an

output is in current limit, it is possible that its voltage can

drop below the UV threshold which also shuts down all

outputs. If that behavior is not desired, just mask the

appropriate fault bit. Note that all faults are masked by

default. Even when the fault are masked, each output

still provides its real-time UV/OV fault status via its fault

flag. Masking an OV/UV fault just prevents the fault from

being reported via the nIRQ pin. A UV/OV fault condition

pulls the nRESET pins low. Note that then nRESET and

nIRQ pins are configurable via CMI settings

Output Current Limit

The ACT88321 incorporates a three-level overcurrent

protection scheme for the buck converters and a single

level scheme for the LDOs. For the buck converters, the

overcurrent current threshold refers to the peak switch

current. The first protection level is when a buck con-

verter’s peak switch current reaches 80% of the Cycle-

by-Cycle current limit threshold for greater than 16

switching cycles. Under this condition, the IC reports the

fault via the appropriate fault flag bit. If the fault is un-

masked, it asserts the nIRQ pin. This may or may not

turn off that output or other outputs depending on the

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