ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

37 of 55

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component selection and optimize transient perfor-

mance over their full operating range. No compensation

design is required; simply follow a few simple guidelines

described below when choosing external components.

Minimum On-Time

The ACT88321 Buck1 minimum on-time is 85ns and the

Buck2/3 minimum on-time is 40ns. If the calculated on-

time is less than the allowable minimum, then the user

must configure the converter to switch at a lower fre-

quency. For Buck1, setting I2C bit HalfFreq = 0 sets Fsw

= 2.25MHz and setting it to 1 sets Fsw = 1.125MHz. For

Buck2/3, the I2C FREQ_SEL bits set Fsw to 1.5MHz,

2.0MHz, 2.5MHz, or 3.3MHz. The following equation

calculates the on-time.

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Where Vout is the output voltage, Vin is the input voltage,

and FSW is the switching frequency.

BUCK1 Bypass Switch

The ACT88321 provides a bypass mode for 3.3V sys-

tems. This allows the 3.3V input voltage to power the

ACT88321 regulators and be sequenced to the down-

stream loads. In bypass mode, the Buck1 P-ch FET acts

as a switch and the N-ch FET is disabled. The bypass

switch turns on the 3.3V rail with the programmed delay

and softstart time.

In bypass mode, the ACT88321 Buck1 I2C registers are

reconfigured to the following settings.

1.

POK register bit is reconfigured to be the output

of the Soft Start ramp. When soft start is com-

plete and the voltage on the SW1 pin reaches

VIN_B1-200mV, this bit goes high to allow the

sequencing of the other regulators to continue.

The POK bit no longer reports the Buck1 output

voltage status.

2.

ILIM register bit is reconfigured to be the output

of the internal PMOS Current Detection circuit.

This is set to 4.5A typical. If the bypass current

exceeds the Internal PMOS Current Detection

current, ILIM triggers the nIRQ output and gets

latched in the ILIM0 bit if IRQ_nMASK = 1 (not

masked). Overcurrent can also be masked with

the

ILIM_FLTMSK

register.

Note

that

ILIM_FLTMSK,

ILIM_WARN_FLTMSK,

OV_FLTMSK and UV_FLTMSK default to 1

(masked) at power up. The user can un-mask

faults by setting these bits to 0 via I2C.

3.

The POK register bit is reconfigured to the out-

put of the Internal PMOS circuit. The voltage

threshold is set to VIN_B1-200mV rising and

VIN_B1-300mV falling. If the bypass switch out-

put goes below this value, it triggers an under-

voltage fault condition and moves the IC into

the OVUVFLT state. This immediately shuts

down all regulators including the bypass switch.

The system restarts in 100ms, following the

programmed startup sequencing. This fault is

disabled by default but can be enabled by set-

ting the I2C bit UV_FLTMSK = 0.

Note that in bypass mode, the overvoltage protection is

set to 3.8V with a 10µs deglitch time. If AVIN goes

above 3.8V, the bypass switch is turned off and retries

after 100ms If OV_FLTMSK=0 and DISOVUVSD=0

Buck1 can be configured to enter bypass mode with a

GPIO pin. With this configuration, the GPIO is called the

MODE pin. Pulling MODE low puts Buck1 in Buck mode.

Pulling MODE high puts Buck1 in bypass mode. Note

that the MODE pin must be fixed either high or low at

startup and that it cannot be changed on-the-fly.

Input Capacitor Selection

Each regulator requires a high quality, low-ESR,

ceramic input capacitor. Note that even though each

buck converter has separate input pins, all input pins

must be connected to the same voltage potential. 10µF

capacitors are typically suitable, but this value can

be increased without limit. Smaller capacitor values

can be used with lighter output loads. Choose the input

capacitor value to keep the input voltage ripple less

than 50mV.

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Be sure to consider the capacitor’s DC bias effects and

maximum ripple current rating when using capacitors

smaller than 0805.

A capacitor’s actual capacitance is strongly affected by

its DC bias characteristics. The input capacitor is

typically an X5R, X7R, or similar dielectric. Use of Y5U,

Z5U, or similar dielectrics is not recommended. Input

capacitor placement is critical for proper operation.

Each buck’s input capacitor must be placed as close to

the IC as possible. The traces from VIN_Bx to the