ACT88321 datasheet(36/55 Pages) QORVO

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ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

36 of 55

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Because Buck2/3 operate in ACOT mode, they require

a minimum off-time every switching cycle. The required

off-time is 40ns. Buck3 has an additional option that al-

lows almost 100% duty cycle when VIN is close to

VOUT. This option, frequency foldback, starts increas-

ing the on-time when the input voltage drops below 125%

of the programmed output voltage. This effectively re-

duces the switching frequency. As the input voltage

drops, the on-time increases until it reaches the maxi-

mum allowable on-time of 3.5µs. This results in >98%

duty cycle with a switching frequency of 285kHz, which

supports very low dropout voltages. Enable this option

by setting EN_FRQ_FB_HDTY=1.

Dynamic Voltage Scaling

Buck2 supports Dynamic Voltage Scaling (DVS). DVS

allows the user to optimize the processor’s energy to

complete tasks by lowering the processor’s operating

frequency and input voltage when lower performance is

acceptable. In normal operation, each output regulates

to the voltage programmed in its I2C register VSET0.

During DVS, the output regulates to VSET1. The output

transitions from VSET0 to VSET1 at a rate determined

by the output capacitance and the load current. The out-

puts transition between VSET1 and VSET0 by the rate

determined by the I2C bits DVS_SET. VSET1 must al-

ways be set equal to or lower than VSET0.

For fault free operation, the user must ensure output

load conditions plus the current required to charge the

output capacitance during a DVS rising voltage condi-

tion does not exceed the current limit setting of the reg-

ulator. As with any power supply, changing an output

voltage too fast can require a current higher than the

current limit setting. The user must ensure that the volt-

age step, slew rate, and load current conditions do not

result in an instantaneous loading that results in a cur-

rent limit condition.

Optimizing Noise

The internal FET rise and fall times can be optimized to

minimize switching noise at the cost of lower efficiency

via the DRVADJ I2C bit.

Overcurrent and Short Circuit Protection

Each buck converter provides overcurrent and short cir-

cuit protection. Overcurrent protection is achieved with

cycle-by-cycle current limiting. The peak current thresh-

old is set by the ILIM_SET I2C bits.

For Buck1, if the peak switch current reaches the pro-

grammed threshold for 16 consecutive switching cycles,

the IC asserts the Buck1 ILIM_WARN bit and pulls nIRQ

low. A short circuit condition that results in the peak

switch current being 122% of the value set by ILIM_SET

immediately shuts down all supplies, asserts the ILIM

bit, and restarts the system in 100ms when EN_ILIM2

(0x4Dh[5])=1, ILIM_FLTMSK=0 and DISOVUVSD=0.

BUCK1 automatically tries to restart in 14ms if

EN_ILIM2=1 and its faults are masked.

For Buck2/3, if the peak switch current reaches the pro-

grammed threshold for 16 consecutive switching cycles,

the IC asserts the Buck2/3 ILIM bit and asserts nIRQ

low. If the short circuit condition lasts for 32 consecutive

switching cycles, the IC immediately shuts down all sup-

plies and restarts the system in 100ms. If Buck2 or

Buck3’s

EN_ILIMSD=1,

ILIM_FLTMSK=0

and

DISOVUVSD=0, the output automatically tries to restart

in 14ms if EN_ILIMSD=1 and it faults are masked.

When an overcurrent condition is reported in the ILIM

I2C registers, the contents of these registers are latched

until read via I2C. Overcurrent and short circuit condi-

tions can be masked via the I2C bit ILIM_FLTMSK. Note

that ILIM_FLTMSK, ILIM_WARN_FLTMSK, OV_FLT-

MSK and UV_FLTMSK default to 1 (masked) at power

up. The user can un-mask faults by setting these bits to

0 via I2C.

After a buck converter starts up (internal POK=1), if its

output voltage drops below the POK falling threshold

longer than the blanking time (~28µs to 56µs), the con-

verter enters foldback current mode. This reduces the

current limit to 1.25A to reduce output voltage overshoot

when the load current drops and the converter recovers

from the short circuit condition.

When the on-time is less than 120ns, the high side FET

overcurrent circuitry will not have enough time to react.

All buck converters include a low-side current limit set-

ting, to account for this condition. The low-side current

limit can only be enabled with a factory setting. When

this current limit threshold is reached, the low side FET

stays on until the inductor current decays lower than the

programmed current threshold. The high side FET can-

not turn on again until the low side FET current drops

below this value. The Buck1/2 low side overcurrent

thresholds are 3.8A when ILIM=0 and 5.0A when

ILIM=1. The Buck3 low side overcurrent threshold is

2.0A when ILIM=0 and 3.0A when ILIM=1. This function

also protects the inductor by preventing current runa-

way which could saturate the inductor.

Compensation

The buck converters utilize a proprietary internal com-

pensation scheme to simultaneously simplify external

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