ACT88321 datasheet(24/55 Pages) QORVO

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ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

24 of 55

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important to note any transition to RESET returns all

volatile and non-volatile registers to their default states

POWER SEQUENCE START State

The POWER SEQUENCE START state is a transitional

state while the regulators are starting. The outputs are

enabled and are starting up in this state. The IC imme-

diately transitions to the POWER ON or SLEEP states

when the regulators go into regulation. The ACT88321

fault mask bits ILIM_FLTMSK, ILIM_WARN_FLTMSK,

OV_FLTMSK and UV_FLTMSK default to 1 at startup,

so if one regulator has a fault at startup, all other regu-

lators will turn on. After a successful power up, these

bits are cleared to 0 so that faults are detected. Any

faults after this time result in standard hiccup mode

functionality.

POWER ON (Active) State

The ACTIVE state is the normal operating state when

the input voltage is within the allowable range, all out-

puts are turned on, and no faults are present. The IC

only enters the ACTIVE State from the POWER SE-

QUENCE START State.

SLEEP State

The SLEEP state is a configurable low power state.

Based on the system’s low power operational require-

ments, the user can configure the SLEEP state by de-

fining which internal and external regulators are kept on

or turned off during the SLEEP state. Each individual

regulator output can be programmed to be either on or

off in the SLEEP state. Buck2 can also be programmed

to regulate to its VSET0 voltage, VSET1 voltage (DVS),

or be turned off in the SLEEP state. Note that no other

regulators can be programmed to change between

VSET0 and VSET1 when the IC enters the SLEEP

State. The regulators follow their programmed sequenc-

ing delay times when turning on or off as they exit or

enter the SLEEP state. The IC can enter SLEEP state

via the I2C register SLEEP bit or by a GPIO input. Figure

3 shows how the NVM SLEEP_MODE factory bit sets

the I2C and GPIO requirements to enter and exit the

SLEEP state.

When the I2C bit SLEEP_MODE = 0, the IC enters

SLEEP State with the logical AND of the I2C SLEEP bit

and the GPIOs. If more than one GPIO is configured as

a SLEEP State input, then all the GPIOs must be as-

serted. If no GPIOs are configured to control the SLEEP

State, then only the SLEEP bit controls SLEEP State

entry and exit. The IC immediately exits the SLEEP

State when the SLEEP bit or a GPIO is de-asserted.

When the I2C bit SLEEP_MODE = 1, the IC enters

SLEEP State with the logical OR of the I2C SLEEP bit

and the GPIOs. If no GPIOs are configured to control

the SLEEP state, then only the SLEEP bit controls the

SLEEP State. The IC exits SLEEP State when both I2C

and GPIO are de-asserted.

GPIOx

SLEEP

ENTER the

SLEEP State

GPIOx

SLEEP

SLEEP State Conditions with

SLEEP_MODE = 0

SLEEP State Conditions with

SLEEP_MODE = 1

DPSLP State Conditions with

DPSLP_MODE = 0

ENTER the

SLEEP State

DPSLP State Conditions with

DPSLP_MODE = 1

GPIOx

DPSLP

ENTER the

DPSLP State

GPIOx

DPSLP

ENTER the

DPSLP State

Figure 3. SLEEP and DPSLP State Truth Tables

DPSLP State

The DPSLP State is another low power operating mode

for the operating system. It is intended to be used in a

lower power configuration than the SLEEP state. It is

similar with the SLEEP state, but DPSLP uses slightly

different configurations to enter and exit this mode.

Each output can be programmed to be on or off in the

DPSLP state. Buck2 can also be programed to operate

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