ACT88321 datasheet(25/55 Pages) QORVO

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ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

25 of 55

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at its VSET0 voltage, VSET1 voltage, or be turned off.

Note that no other regulators can be programmed to

change between VSET0 and VSET1 when the IC enters

the SLEEP State. All outputs can be programmed to

have different functionality between the SLEEP and

DPSLP states. The outputs follow their programmed se-

quencing delay times when turning on or off as they en-

ter or exit the DPSLP state. The IC can enter DPSLP

state via the I2C register DPSLP bit or by a GPIOs input.

Figure 3 shows how the NVM DPSLP factory bit sets

the I2C and GPIO requirements to enter and exit the

DPSLP state.

Any GPIO can be configured to control the DPSLP state

without requiring any I2C command. This GPIO hard-

ware function is called PWREN. After the DPSLP state

is enabled via I2C, a high to low transition on the

PWREN input puts the IC in DPSLP state. When the

PWREN input is toggled from low to high, the IC exits

DPSLP state.

The PWREN function can be configured to be either

edge triggered or level triggered. The difference be-

tween these configurations only affects DPSLP Mode at

power up.

Level triggered: If PWREN is low at startup, the IC en-

ters DPSLP immediately after VIN goes above the UV

threshold.

Edge triggered: If PWREN is low at startup, the IC ig-

nores PWREN and starts up normally. PWREN must be

pulled high and then pulled low to enter DPSLP Mode.

If PWREN is high at startup, the IC immediately enters

DPSLP Mode when PWREN is pulled low.

the

SLEEP

state,

NVM

factory

bit

DPSLP_MODE sets the logic OR or AND logic between

I2C and GPIOs for entering and exiting the DPSLP state.

When DPSLP_MODE = 0, the IC enters DPSLP State

with the logical AND of the I2C DPSLP bit and the

GPIOs. If more than one GPIO is configured as a

DPSLP State input, then all the GPIOs must be as-

serted. If no GPIOs are configured to control the DPSLP

State, then only the DPSLP bit controls DPSLP State

entry and exit. The IC immediately exits the DPSLP

State when the DPSLP bit or a GPIO is de-asserted.

When the I2C bit DPSLP_MODE = 1, the IC enters

DPSLP State with the logical OR of the I2C DPSLP bit

and the GPIOs. If no GPIOs are configured to control

the DPSLP state, then only the DPSLP bit controls the

DPSLP State. The IC exits DPSLP State when both I2C

and GPIO are de-asserted.

GPIOs can also be programmed to individually turn one

or multiple outputs on and off. This on/off GPIO func-

tionality in addition to the PWREN functionality. It pro-

vides a wide range of configurability for setting different

DPSLP on/off patterns. Note that the GPIOs have four

delay time options for both the rising and falling edges.

These settings are 0ms, 1ms, 2.5ms, and 5ms.

For example, in SSD applications, the host can use

these GPIOs and PWREN to enter different power save

modes like PS3.5 and PS4.

In video applications, the GPIOs can be connected to

sensor inputs to trigger the IC to exit the DPSLP mode

when a sensor input triggers. The GPIO polarity can be

programmed as active HIGH or LOW. GPIOs also have

a programmable 1ms, 5ms, and 10ms deglitch time.

THERMAL State

In the THERMAL state, the IC has exceeded the ther-

mal shutdown temperature. The IC shuts down all reg-

ulators and asserts the nRESET to protect the IC in this

condition. The THERMAL state can be disabled by set-

ting register 0x01h bit 5 (TMSK) = 1. Note that thermal

shutdown fault bit, TWARN, still provides the thermal

status even if TMSK = 1.

OVUVFLT State

If one of the regulators exceed an OV or UV level at any

time after the soft start ramp has completed, the IC

moves to UVOVFLT state. In this state, all regulators

shutdown and the IC asserts the nRESET pin. After en-

tering the OVUVFLT state, the IC stays there for 100ms

and then goes back to the ACTIVE state. If the OV or

UV condition still exists in the ACTIVE state, the IC re-

turns to the OVUVFLT state. The cycle continues until

the OV or UV fault is removed, or the input power is re-

moved. This state can only be enabled by clearing an

output’s OV_FLTMSK or UV_FLTMSK volatile bits to 0

and setting DISOVUVSD(0x09h[0])=0. The IC does not

directly enter OVUVFLT in an overcurrent condition but

does enter this state due to the resulting UV condition.

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