ACT88321 datasheet(23/55 Pages) QORVO

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ACT88321

Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches

Datasheet Rev. D , June 17, 2022 | Subject to change without notice

23 of 55

www.qorvo.com

SYSTEM CONTROL INFORMATION

General

The ACT88321 is a single-chip integrated power man-

agement solution designed to power many processors.

It integrates three highly efficient buck regulators, and

two LDOs. Its high integration and high switching fre-

quency result in an extremely small footprint and low-

cost power solution. It contains a master controller that

manages startup sequencing, timing, voltages, slew

rates, sleep states, and fault conditions. I2C configura-

bility allows system level changes without the need for

costly PCB changes. The built-in load bypass switch en-

ables full sequencing configurability in 3.3V systems.

The ACT88321 master controller monitors all outputs

and reports faults via I2C and hardwired status signals.

Faults can be masked, and fault levels and responses

are configurable via I2C.

Many of the ACT88321 GPIOs and functions are con-

figurable. The IC’s default functionality is defined by the

default CMI (Code Matrix Index), but much of this func-

tionality can be changed via I2C. The first part of the

datasheet describes basic IC functionality and default

pin functions. The last section of the datasheet provides

the configuration and functionality specific to each CMI

version. Contact sales@qorvo.com for additional infor-

mation about other configurations.

I2C Serial Interface

To ensure compatibility with a wide range of systems,

the ACT88321 uses standard I2C commands. The

ACT88321 always operates as a slave device and is ad-

dressed using a 7-bit slave address followed by an

eighth bit, which indicates whether the transaction is a

read-operation or a write-operation. Refer to each spe-

cific CMI for the IC’s slave address

There is no timeout function in the I2C packet pro-

cessing state machine, however, any time the I2C state

machine receives a start bit command, it immediately

resets the packet processing, even if it is in the middle

of a valid packet.

I2C commands are communicated using the SCL and

SDA pins. SCL is the I2C serial clock input. SDA is the

data input and output. SDA is open drain and must have

a pullup resistor. Signals on these pins must meet tim-

ing requirements in the Electrical Characteristics Table.

Table 1: ACT88321 I2C Addresses

7-Bit Slave Address

8-Bit Write

Address

8-Bit Read

Address

0x25h

010 0101b

0x4Ah

0x4Bh

0x27h

010 0111b

0x4Eh

0x4Fh

0x67h

110 0111b

0xCEh

0xCFh

0x6Bh

110 1011b

0xD6h

0xD7h

I2C Registers

The ACT88321 has an array of internal registers that

contain the IC’s basic instructions for setting up the IC

configuration, output voltages, switching frequency,

fault thresholds, fault masks, etc. These registers give

the IC its operating flexibility. The two types of registers

are described below.

Basic Volatile – These are R/W (Read and Write) and

RO (Read only). After the IC is powered, the user can

modify the R/W register values to change IC functional-

ity. Changes in functionality include things like masking

certain faults. The RO registers communicate IC status

such as fault conditions. Any changes to these registers

are lost when power is recycled. The default values are

fixed and cannot be changed by the factory or the end

user.

Basic Non-Volatile – These are R/W and RO. After the

IC is powered, the user can modify the R/W register val-

ues to change IC functionality. Changes in functionality

include things like output voltage settings, startup delay

time, and current limit thresholds. Any changes to these

registers are lost when power is recycled. The default

values can be modified at the factory to optimize IC

functionality for specific applications. Please contact

Qorvo for custom options and minimum order quantities.

When modifying only certain bits within a register, take

care to not inadvertently change other bits. Inadvert-

ently changing register contents can lead to unexpected

device behavior.

State Machine

The ACT88321 contains an internal state machine with

five internal states.

RESET State

In the RESET, or “cold” state, the ACT88321 is waiting

for the input voltage on AVIN to be within a valid range

defined by the UVLO and VIN_OV thresholds. All vola-

tile registers are reset to defaults and Non-Volatile reg-

isters are reset to programmed defaults. The IC transi-

tions from RESET to POWER SEQUENCE START

when the input voltage enters the valid range. The IC

transitions from any other state to RESET if the input

voltage drops below the UVLO threshold voltage. It is

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