XRT86VL32IB datasheet(97/153 Pages) EXAR

97 / 153 page

XRT86VL3X

REV. 1.2.2

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

The Alarm Indication Signal Detection Select bits of the Alarm Generation Register (AGR) enable the two types

of AIS detection that are supported by the XRT86VL3x framer. The table below shows configurations of the

Alarm Indication Signal Detection Select bits of the Alarm Generation Register (AGR).

If detection of unframed or framed AIS alarm is enabled by the user and if AIS is present in the incoming DS1

frame, the XRT86VL3x framer can generate a Receive AIS State Change interrupt associated with the setting

of Receive AIS State Change bit of the Alarm and Error Status Register to one.

To enable the Receive AIS State Change interrupt, the Receive AIS State Change Interrupt Enable bit of the

Alarm and Error Interrupt Enable Register (AEIER) have to be set to one. In addition, the Alarm and Error

Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.

The table below shows configurations of the Receive AIS State Change Interrupt Enable bit of the Alarm and

Error Interrupt Enable Register (AEIER).

The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable

When these interrupt enable bits are set and AIS is present in the incoming DS1 frame, the XRT86VL3x framer

will declare AIS by doing the following:

• Set the read-only Receive AIS State bit of the Alarm and Error Status Register (AESR) to one indicating

there is AIS alarm detected in the incoming DS1 frame.

• Set the Receive AIS State Change bit of the Alarm and Error Status Register to one indicating there is a

change in state of AIS. This status indicator is valid until the Framer Interrupt Status Register is read.

Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control

indicators.

ALARM GENERATION REGISTER (AGR) (ADDRESS = 0XN108H)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

1-0

AIS Detection

Select

R/W

00 - AIS alarm detection is disabled.When this bit is set to 01:Detection of

unframed AIS alarm of all ones pattern is enabled.

10 - AIS alarm detection is disabled.When this bit is set to 00:Detection of

framed AIS alarm of all ones pattern except for framing bits is enabled.

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (ADDRESS = 0XNB03H)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

Receive AIS State

Change Interrupt

Enable

R/W

0 - The Receive AIS State Change interrupt is disabled.

1 - The Receive AIS State Change interrupt is enabled.

BLOCK INTERRUPT ENABLE REGISTER (BIER) (ADDRESS = 0XNB01H)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

Alarm and Error

Interrupt Enable

R/W

0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-

ister (AEISR) is disabled.

1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-

ister (AEISR) is enabled.

XRT86VL32IB Datasheet(PDF) 97 Page - Exar Corporation

XRT86VL32IB Datasheet(HTML) 97 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL