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XRT86VL32IB Datasheet(PDF) 16 Page - Exar Corporation |
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XRT86VL32IB Datasheet(HTML) 16 Page - Exar Corporation |
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16 / 153 page  XRT86VL3X 9 T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION REV. 1.2.2 1.7 T1/E1 Fractional Interface The individual time slots can be enabled/disabled to carry fractional DS-0 data. The purpose of this interface is to enable one or more time slots in the PCM data (TxSER) to be replaced with the fractional DS-0 payload. If this mode is selected, the dedicated hardware pin TxCHN1/T1FR is used to input the fractional DS-0 data within the time slots that are enabled. The dedicated hardware pin RxCHN1/R1FR is used to output the fractional DS-0 data within the time slots that are enabled. Figure 9 is a simplified diagram of the Fractional Interface. FIGURE 9. T1 FRACTIONAL INTERFACE TSN - TSM TxCHN1/T1FR TxSERclk TxSYNC TxMSYNC F T1 Fractional Data PCM TS[0-(N-1)] PCM TS[(M+1)-23] TxSER |
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