XRT86VL32IB datasheet(28/153 Pages) EXAR

Part #	XRT86VL32IB

Description	T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

PDF	153 Pages

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Manufacturer	EXAR [Exar Corporation]

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XRT86VL3X

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

REV. 1.2.2

3.1

Storing and Retrieving Message Contents

Each buffer has its own dedicated internal holding register. To access the contents of these buffers or to store

messages, the XRT86VL3x utilizes a multiplexed access. The buffers are broken down into Buffer 0 or Buffer

1. Register 0xn600 is used to Read or Write to Buffer 0 of the selected HDLC controller, while register 0xn700

is used to Read or Write to Buffer 1 of the selected HDLC controller. Although, each HDLC controller has its

own dedicated register set for control, the message contents of only one controller can be accessed at one

time through the microprocessor or DMA interface.

FIGURE 29. STORING AND RETRIEVING MESSAGE CONTENTS

96-Bytes

HDLC1 Buffer 0

96-Bytes

HDLC2 Buffer 0

96-Bytes

HDLC3 Buffer 0

96-Bytes

HDLC1 Buffer 1

96-Bytes

HDLC2 Buffer 1

96-Bytes

HDLC3 Buffer 1

XRT86VL32IB Datasheet(PDF) 28 Page - Exar Corporation