XRT86VL32IB datasheet(59/153 Pages) EXAR

59 / 153 page

XRT86VL3X

REV. 1.2.2

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

5.3.2

DMO (Digital Monitor Output)

The driver monitor circuit is used to detect transmit driver failures by monitoring the activities at TTIP/TRING

outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the

transmit inputs. If the transmitter of a channel has no output for more than 128 clock cycles, DMO goes "High"

until a valid transmit pulse is detected. If the DMO interrupt is enabled, the change in status of DMO will cause

the interrupt pin to go "Low". Once the status register is read, the interrupt pin will return "High" and the status

5.3.3

Transmit Jitter Attenuator

The transmit path has a dedicated jitter attenuator to reduce phase and frequency jitter in the transmit clock.

The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. When

the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the

jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this

condition occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is

outside the 2-Bit window. In T1 mode, the bandwidth of the JA is always set to 3Hz. In E1 mode, the

bandwidth is programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The

JA has a clock delay equal to ½ of the FIFO bit depth.

NOTE: The Receive Path has a dedicated jitter attenuator. See the Receive Path Line Interface Section.

5.4

Line Termination (TTIP/TRING)

The output stage of the transmit path generates standard return-to-zero (RZ) signals to the line interface for T1/

E1/J1 twisted pair or E1 coaxial cable.

The physical interface is optimized by placing the terminating

impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of

external components necessary in system design. The transmitter outputs only require one DC blocking

capacitor of 0.68

μF. For redundancy applications (or simply to tri-state the transmitters), set TxTSEL to a "1" in

the appropriate channel register. A typical transmit interface is shown in Figure 54.

FIGURE 54. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION

TTIP

TRING

XRT86VL3x LIU

1:2

Internal Impedance

Line Interface T1/E1/J1

C=0.68uF

One Bill of Materials

Transmitter

Output

XRT86VL32IB Datasheet(PDF) 59 Page - Exar Corporation

XRT86VL32IB Datasheet(HTML) 59 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL