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XRT86VL32IB Datasheet(PDF) 81 Page - Exar Corporation |
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XRT86VL32IB Datasheet(HTML) 81 Page - Exar Corporation |
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81 / 153 page  XRT86VL3X 74 REV. 1.2.2 T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION The mapping of T1 frame into E1 framing format is shown in the table below. 8.2.2 Non-Multiplexed High-Speed Mode When the Back-plane interface data rate is MVIP 2.048Mbit/s, 4.096Mbit/s and 8.192Mbit/s, the interface signals are all configured as inputs, except the receive serial data on RxSER and the multi frame sync pulse (RxMSYNC) provided by the framer. The Transmit Serial Clock for each channel is always an input clock with frequency of 1.544 MHz for all data rates so that it may be used as the timing reference for the transmit line rate. The TxMSYNC signal is configured as the Transmit Input Clock with frequencies of 2.048 MHz, 4.096 MHz and 8.192 MHz respectively. It serves as the primary clock source for the High-speed Back-plane Interface. Figure 81 shows how to connect the Transmit non-multiplexed high-speed Input Interface block to local Terminal Equipment. Figure 82 shows how to connect the Receive non-multiplexed high-speed Output Interface to local Terminal Equipment. TABLE 6: MAPPING A T1 FRAME INTO AN E1 FRANE T1 F-Bit TS0 TS1 TS2 Don't Care Bits TS3 TS4 TS5 E1 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 T1 Don't Care Bits TS6 TS7 TS8 Don't Care Bits TS9 TS10 TS11 E1 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 T1 Don't Care Bits TS12 TS13 TS14 Don't Care Bits TS15 TS16 TS17 E1 TS16 TS17 TS18 TS19 TS20 TS21 TS22 TS23 T1 Don't Care Bits TS18 TS19 TS20 Don't Care Bits TS21 TS22 TS23 E1 TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31 FIGURE 81. TRANSMIT NON-MULTIPLEXED HIGH-SPEED CONNECTION TO LOCAL TERMINAL EQUIPMENT USING MVIP 2.048MBIT/S, 4.096MBIT/S, OR 8.192MBIT/S TxSERCLK0 TxSER0 TxINCLK0 TxSYNC0 Transmit Payload Data Input Interface Chn 0 Transmit Payload Data Input Interface Chn N Terminal Equipment XRT86VL3x TxSERCLKn TxSERn TxINCLKn TxSYNCn TxINCLK = 2.048/4.096/8.192MHz |
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