XRT86VL32IB datasheet(67/153 Pages) EXAR

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XRT86VL3X

REV. 1.2.2

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

7.2

Transmit/Receive High-Speed Back-Plane Interface

The High-speed Back-plane Interface supports payload data to be taken from or presented to the Terminal

Equipment at different data rates. In the non-multiplexed mode, payload data of each channel are interfaced to

the Terminal Equipment separately.

Each channel uses its own serial clock, serial data, single-frame

synchronization signal and multi-frame synchronization signals.

7.2.1

Non-Multiplexed High-Speed Mode

When the Back-plane interface data rate is MVIP 2.048Mbit/s, 4.096Mbit/s and 8.192Mbit/s, the interface

signals are all configured as inputs, except the receive serial data on RxSER and the multi frame sync pulse

provided by the framer. The Transmit Serial Clock for each channel is always an input clock with frequency of

2.048 MHz for all data rates so that it may be used as the timing reference for the transmit line rate. The

TxMSYNC signal is configured as the Transmit Input Clock with frequencies of 2.048 MHz, 4.096 MHz and

8.192 MHz respectively. It serves as the primary clock source for the High-speed Back-plane Interface.

Figure 65

shows how to connect the Transmit non-multiplexed high-speed Input Interface block to local

Terminal Equipment.

Figure 66

shows how to connect the Receive non-multiplexed high-speed Output

Interface to local Terminal Equipment.

FIGURE 64. WAVEFORMS FOR CONNECTING THE RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK TO LOCAL TER-

MINAL

EQUIPMENT

RxSerClk

RxSer

RxSync(output)

RxCHClk

RxCHN[4:0]

RxCHN[0]/RxSig

RxCHClk

RxCHN[2]/RxChn

RxCHN[1]/RxFrTD

c1 c2 c3 c4 c5

A B

Input Data

Timeslot 31

Timeslot 0

Timeslot 5

Timeslot 6

Timeslot #0

Timeslot #5

Timeslot #6

Timeslot #31

Rx Fractional Enable Bit = 0

Rx Fractional Enable Bit = 1

XRT86VL32IB Datasheet(PDF) 67 Page - Exar Corporation

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